1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2008 Openmoko, Inc. 4*4882a593Smuzhiyun * Copyright 2008 Simtec Electronics 5*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 6*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * S3C64XX clock register definitions 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __PLAT_REGS_CLOCK_H 12*4882a593Smuzhiyun #define __PLAT_REGS_CLOCK_H __FILE__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * FIXME: Remove remaining definitions 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define S3C_CLKREG(x) (S3C_VA_SYS + (x)) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define S3C_PCLK_GATE S3C_CLKREG(0x34) 21*4882a593Smuzhiyun #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) 22*4882a593Smuzhiyun #define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* PCLK GATE Registers */ 25*4882a593Smuzhiyun #define S3C_CLKCON_PCLK_UART3 (1<<4) 26*4882a593Smuzhiyun #define S3C_CLKCON_PCLK_UART2 (1<<3) 27*4882a593Smuzhiyun #define S3C_CLKCON_PCLK_UART1 (1<<2) 28*4882a593Smuzhiyun #define S3C_CLKCON_PCLK_UART0 (1<<1) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* MEM_SYS_CFG */ 31*4882a593Smuzhiyun #define MEM_SYS_CFG_INDEP_CF 0x4000 32*4882a593Smuzhiyun #define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* _PLAT_REGS_CLOCK_H */ 35