1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> 4*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * S3C2410 clock register definitions 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARM_REGS_CLOCK 10*4882a593Smuzhiyun #define __ASM_ARM_REGS_CLOCK 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "map.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define S3C2410_LOCKTIME S3C2410_CLKREG(0x00) 19*4882a593Smuzhiyun #define S3C2410_MPLLCON S3C2410_CLKREG(0x04) 20*4882a593Smuzhiyun #define S3C2410_UPLLCON S3C2410_CLKREG(0x08) 21*4882a593Smuzhiyun #define S3C2410_CLKCON S3C2410_CLKREG(0x0C) 22*4882a593Smuzhiyun #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) 23*4882a593Smuzhiyun #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define S3C2410_CLKCON_IDLE (1<<2) 26*4882a593Smuzhiyun #define S3C2410_CLKCON_POWER (1<<3) 27*4882a593Smuzhiyun #define S3C2410_CLKCON_NAND (1<<4) 28*4882a593Smuzhiyun #define S3C2410_CLKCON_LCDC (1<<5) 29*4882a593Smuzhiyun #define S3C2410_CLKCON_USBH (1<<6) 30*4882a593Smuzhiyun #define S3C2410_CLKCON_USBD (1<<7) 31*4882a593Smuzhiyun #define S3C2410_CLKCON_PWMT (1<<8) 32*4882a593Smuzhiyun #define S3C2410_CLKCON_SDI (1<<9) 33*4882a593Smuzhiyun #define S3C2410_CLKCON_UART0 (1<<10) 34*4882a593Smuzhiyun #define S3C2410_CLKCON_UART1 (1<<11) 35*4882a593Smuzhiyun #define S3C2410_CLKCON_UART2 (1<<12) 36*4882a593Smuzhiyun #define S3C2410_CLKCON_GPIO (1<<13) 37*4882a593Smuzhiyun #define S3C2410_CLKCON_RTC (1<<14) 38*4882a593Smuzhiyun #define S3C2410_CLKCON_ADC (1<<15) 39*4882a593Smuzhiyun #define S3C2410_CLKCON_IIC (1<<16) 40*4882a593Smuzhiyun #define S3C2410_CLKCON_IIS (1<<17) 41*4882a593Smuzhiyun #define S3C2410_CLKCON_SPI (1<<18) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define S3C2410_CLKDIVN_PDIVN (1<<0) 44*4882a593Smuzhiyun #define S3C2410_CLKDIVN_HDIVN (1<<1) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define S3C2410_CLKSLOW_UCLK_OFF (1<<7) 47*4882a593Smuzhiyun #define S3C2410_CLKSLOW_MPLL_OFF (1<<5) 48*4882a593Smuzhiyun #define S3C2410_CLKSLOW_SLOW (1<<4) 49*4882a593Smuzhiyun #define S3C2410_CLKSLOW_SLOWVAL(x) (x) 50*4882a593Smuzhiyun #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* extra registers */ 55*4882a593Smuzhiyun #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define S3C2440_CLKCON_CAMERA (1<<19) 58*4882a593Smuzhiyun #define S3C2440_CLKCON_AC97 (1<<20) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define S3C2440_CLKDIVN_PDIVN (1<<0) 61*4882a593Smuzhiyun #define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) 62*4882a593Smuzhiyun #define S3C2440_CLKDIVN_HDIVN_1 (0<<1) 63*4882a593Smuzhiyun #define S3C2440_CLKDIVN_HDIVN_2 (1<<1) 64*4882a593Smuzhiyun #define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) 65*4882a593Smuzhiyun #define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) 66*4882a593Smuzhiyun #define S3C2440_CLKDIVN_UCLK (1<<3) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) 69*4882a593Smuzhiyun #define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) 70*4882a593Smuzhiyun #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) 71*4882a593Smuzhiyun #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) 72*4882a593Smuzhiyun #define S3C2440_CAMDIVN_DVSEN (1<<12) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #if defined(CONFIG_CPU_S3C2412) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define S3C2412_OSCSET S3C2410_CLKREG(0x18) 81*4882a593Smuzhiyun #define S3C2412_CLKSRC S3C2410_CLKREG(0x1C) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define S3C2412_PLLCON_OFF (1<<20) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define S3C2412_CLKDIVN_PDIVN (1<<2) 86*4882a593Smuzhiyun #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) 87*4882a593Smuzhiyun #define S3C2412_CLKDIVN_ARMDIVN (1<<3) 88*4882a593Smuzhiyun #define S3C2412_CLKDIVN_DVSEN (1<<4) 89*4882a593Smuzhiyun #define S3C2412_CLKDIVN_HALFHCLK (1<<5) 90*4882a593Smuzhiyun #define S3C2412_CLKDIVN_USB48DIV (1<<6) 91*4882a593Smuzhiyun #define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) 92*4882a593Smuzhiyun #define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) 93*4882a593Smuzhiyun #define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12) 94*4882a593Smuzhiyun #define S3C2412_CLKDIVN_I2SDIV_SHIFT (12) 95*4882a593Smuzhiyun #define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16) 96*4882a593Smuzhiyun #define S3C2412_CLKDIVN_CAMDIV_SHIFT (16) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define S3C2412_CLKCON_WDT (1<<28) 99*4882a593Smuzhiyun #define S3C2412_CLKCON_SPI (1<<27) 100*4882a593Smuzhiyun #define S3C2412_CLKCON_IIS (1<<26) 101*4882a593Smuzhiyun #define S3C2412_CLKCON_IIC (1<<25) 102*4882a593Smuzhiyun #define S3C2412_CLKCON_ADC (1<<24) 103*4882a593Smuzhiyun #define S3C2412_CLKCON_RTC (1<<23) 104*4882a593Smuzhiyun #define S3C2412_CLKCON_GPIO (1<<22) 105*4882a593Smuzhiyun #define S3C2412_CLKCON_UART2 (1<<21) 106*4882a593Smuzhiyun #define S3C2412_CLKCON_UART1 (1<<20) 107*4882a593Smuzhiyun #define S3C2412_CLKCON_UART0 (1<<19) 108*4882a593Smuzhiyun #define S3C2412_CLKCON_SDI (1<<18) 109*4882a593Smuzhiyun #define S3C2412_CLKCON_PWMT (1<<17) 110*4882a593Smuzhiyun #define S3C2412_CLKCON_USBD (1<<16) 111*4882a593Smuzhiyun #define S3C2412_CLKCON_CAMCLK (1<<15) 112*4882a593Smuzhiyun #define S3C2412_CLKCON_UARTCLK (1<<14) 113*4882a593Smuzhiyun /* missing 13 */ 114*4882a593Smuzhiyun #define S3C2412_CLKCON_USB_HOST48 (1<<12) 115*4882a593Smuzhiyun #define S3C2412_CLKCON_USB_DEV48 (1<<11) 116*4882a593Smuzhiyun #define S3C2412_CLKCON_HCLKdiv2 (1<<10) 117*4882a593Smuzhiyun #define S3C2412_CLKCON_HCLKx2 (1<<9) 118*4882a593Smuzhiyun #define S3C2412_CLKCON_SDRAM (1<<8) 119*4882a593Smuzhiyun /* missing 7 */ 120*4882a593Smuzhiyun #define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH 121*4882a593Smuzhiyun #define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC 122*4882a593Smuzhiyun #define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND 123*4882a593Smuzhiyun #define S3C2412_CLKCON_DMA3 (1<<3) 124*4882a593Smuzhiyun #define S3C2412_CLKCON_DMA2 (1<<2) 125*4882a593Smuzhiyun #define S3C2412_CLKCON_DMA1 (1<<1) 126*4882a593Smuzhiyun #define S3C2412_CLKCON_DMA0 (1<<0) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* clock sourec controls */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0) 131*4882a593Smuzhiyun #define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0) 132*4882a593Smuzhiyun #define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3) 133*4882a593Smuzhiyun #define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4) 134*4882a593Smuzhiyun #define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5) 135*4882a593Smuzhiyun #define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8) 136*4882a593Smuzhiyun #define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) 137*4882a593Smuzhiyun #define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) 138*4882a593Smuzhiyun #define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) 139*4882a593Smuzhiyun #define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) 140*4882a593Smuzhiyun #define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #endif /* CONFIG_CPU_S3C2412 */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* __ASM_ARM_REGS_CLOCK */ 147