1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2004-2006 Simtec Electronics
4*4882a593Smuzhiyun // Ben Dooks <ben@simtec.co.uk>
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // S3C24XX Power Manager (Suspend-To-RAM) support
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // See Documentation/arm/samsung-s3c24xx/suspend.rst for more information
9*4882a593Smuzhiyun //
10*4882a593Smuzhiyun // Parts based on arch/arm/mach-pxa/pm.c
11*4882a593Smuzhiyun //
12*4882a593Smuzhiyun // Thanks to Dimitry Andric for debugging
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/suspend.h>
16*4882a593Smuzhiyun #include <linux/errno.h>
17*4882a593Smuzhiyun #include <linux/time.h>
18*4882a593Smuzhiyun #include <linux/gpio.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <linux/serial_core.h>
21*4882a593Smuzhiyun #include <linux/serial_s3c.h>
22*4882a593Smuzhiyun #include <linux/io.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "regs-clock.h"
25*4882a593Smuzhiyun #include "regs-gpio.h"
26*4882a593Smuzhiyun #include "regs-irq.h"
27*4882a593Smuzhiyun #include "gpio-samsung.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include <asm/mach/time.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include "gpio-cfg.h"
32*4882a593Smuzhiyun #include "pm.h"
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include "regs-mem-s3c24xx.h"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define PFX "s3c24xx-pm: "
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
39*4882a593Smuzhiyun static struct sleep_save core_save[] = {
40*4882a593Smuzhiyun /* we restore the timings here, with the proviso that the board
41*4882a593Smuzhiyun * brings the system up in an slower, or equal frequency setting
42*4882a593Smuzhiyun * to the original system.
43*4882a593Smuzhiyun *
44*4882a593Smuzhiyun * if we cannot guarantee this, then things are going to go very
45*4882a593Smuzhiyun * wrong here, as we modify the refresh and both pll settings.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun SAVE_ITEM(S3C2410_BWSCON),
49*4882a593Smuzhiyun SAVE_ITEM(S3C2410_BANKCON0),
50*4882a593Smuzhiyun SAVE_ITEM(S3C2410_BANKCON1),
51*4882a593Smuzhiyun SAVE_ITEM(S3C2410_BANKCON2),
52*4882a593Smuzhiyun SAVE_ITEM(S3C2410_BANKCON3),
53*4882a593Smuzhiyun SAVE_ITEM(S3C2410_BANKCON4),
54*4882a593Smuzhiyun SAVE_ITEM(S3C2410_BANKCON5),
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* s3c_pm_check_resume_pin
59*4882a593Smuzhiyun *
60*4882a593Smuzhiyun * check to see if the pin is configured correctly for sleep mode, and
61*4882a593Smuzhiyun * make any necessary adjustments if it is not
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun
s3c_pm_check_resume_pin(unsigned int pin,unsigned int irqoffs)64*4882a593Smuzhiyun static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun unsigned long irqstate;
67*4882a593Smuzhiyun unsigned long pinstate;
68*4882a593Smuzhiyun int irq = gpio_to_irq(pin);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (irqoffs < 4)
71*4882a593Smuzhiyun irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
72*4882a593Smuzhiyun else
73*4882a593Smuzhiyun irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun pinstate = s3c_gpio_getcfg(pin);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (!irqstate) {
78*4882a593Smuzhiyun if (pinstate == S3C2410_GPIO_IRQ)
79*4882a593Smuzhiyun S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
80*4882a593Smuzhiyun } else {
81*4882a593Smuzhiyun if (pinstate == S3C2410_GPIO_IRQ) {
82*4882a593Smuzhiyun S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
83*4882a593Smuzhiyun s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* s3c_pm_configure_extint
89*4882a593Smuzhiyun *
90*4882a593Smuzhiyun * configure all external interrupt pins
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun
s3c_pm_configure_extint(void)93*4882a593Smuzhiyun void s3c_pm_configure_extint(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun int pin;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* for each of the external interrupts (EINT0..EINT15) we
98*4882a593Smuzhiyun * need to check whether it is an external interrupt source,
99*4882a593Smuzhiyun * and then configure it as an input if it is not
100*4882a593Smuzhiyun */
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
103*4882a593Smuzhiyun s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
107*4882a593Smuzhiyun s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
s3c_pm_restore_core(void)112*4882a593Smuzhiyun void s3c_pm_restore_core(void)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
s3c_pm_save_core(void)117*4882a593Smuzhiyun void s3c_pm_save_core(void)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun #endif
122