1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2008 Openmoko, Inc. 4*4882a593Smuzhiyun * Copyright 2008 Simtec Electronics 5*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 6*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __MACH_S3C64XX_PM_CORE_H 12*4882a593Smuzhiyun #define __MACH_S3C64XX_PM_CORE_H __FILE__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/serial_s3c.h> 15*4882a593Smuzhiyun #include <linux/delay.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "regs-gpio.h" 18*4882a593Smuzhiyun #include "regs-clock.h" 19*4882a593Smuzhiyun #include "map.h" 20*4882a593Smuzhiyun s3c_pm_debug_init_uart(void)21*4882a593Smuzhiyunstatic inline void s3c_pm_debug_init_uart(void) 22*4882a593Smuzhiyun { 23*4882a593Smuzhiyun #ifdef CONFIG_SAMSUNG_PM_DEBUG 24*4882a593Smuzhiyun u32 tmp = __raw_readl(S3C_PCLK_GATE); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* As a note, since the S3C64XX UARTs generally have multiple 27*4882a593Smuzhiyun * clock sources, we simply enable PCLK at the moment and hope 28*4882a593Smuzhiyun * that the resume settings for the UART are suitable for the 29*4882a593Smuzhiyun * use with PCLK. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun tmp |= S3C_CLKCON_PCLK_UART0; 33*4882a593Smuzhiyun tmp |= S3C_CLKCON_PCLK_UART1; 34*4882a593Smuzhiyun tmp |= S3C_CLKCON_PCLK_UART2; 35*4882a593Smuzhiyun tmp |= S3C_CLKCON_PCLK_UART3; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun __raw_writel(tmp, S3C_PCLK_GATE); 38*4882a593Smuzhiyun udelay(10); 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun } 41*4882a593Smuzhiyun s3c_pm_arch_prepare_irqs(void)42*4882a593Smuzhiyunstatic inline void s3c_pm_arch_prepare_irqs(void) 43*4882a593Smuzhiyun { 44*4882a593Smuzhiyun /* VIC should have already been taken care of */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* clear any pending EINT0 interrupts */ 47*4882a593Smuzhiyun __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); 48*4882a593Smuzhiyun } 49*4882a593Smuzhiyun s3c_pm_arch_stop_clocks(void)50*4882a593Smuzhiyunstatic inline void s3c_pm_arch_stop_clocks(void) 51*4882a593Smuzhiyun { 52*4882a593Smuzhiyun } 53*4882a593Smuzhiyun s3c_pm_arch_show_resume_irqs(void)54*4882a593Smuzhiyunstatic inline void s3c_pm_arch_show_resume_irqs(void) 55*4882a593Smuzhiyun { 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* make these defines, we currently do not have any need to change 59*4882a593Smuzhiyun * the IRQ wake controls depending on the CPU we are running on */ 60*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP 61*4882a593Smuzhiyun #define s3c_irqwake_eintallow ((1 << 28) - 1) 62*4882a593Smuzhiyun #define s3c_irqwake_intallow (~0) 63*4882a593Smuzhiyun #else 64*4882a593Smuzhiyun #define s3c_irqwake_eintallow 0 65*4882a593Smuzhiyun #define s3c_irqwake_intallow 0 66*4882a593Smuzhiyun #endif 67*4882a593Smuzhiyun s3c_pm_restored_gpios(void)68*4882a593Smuzhiyunstatic inline void s3c_pm_restored_gpios(void) 69*4882a593Smuzhiyun { 70*4882a593Smuzhiyun /* ensure sleep mode has been cleared from the system */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun __raw_writel(0, S3C64XX_SLPEN); 73*4882a593Smuzhiyun } 74*4882a593Smuzhiyun samsung_pm_saved_gpios(void)75*4882a593Smuzhiyunstatic inline void samsung_pm_saved_gpios(void) 76*4882a593Smuzhiyun { 77*4882a593Smuzhiyun /* turn on the sleep mode and keep it there, as it seems that during 78*4882a593Smuzhiyun * suspend the xCON registers get re-set and thus you can end up with 79*4882a593Smuzhiyun * problems between going to sleep and resuming. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); 83*4882a593Smuzhiyun } 84*4882a593Smuzhiyun #endif /* __MACH_S3C64XX_PM_CORE_H */ 85