1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2006-2007 Simtec Electronics
4*4882a593Smuzhiyun // http://armlinux.simtec.co.uk/
5*4882a593Smuzhiyun // Ben Dooks <ben@simtec.co.uk>
6*4882a593Smuzhiyun // Vincent Sanders <vince@arm.linux.org.uk>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/soc/samsung/s3c-cpufreq-core.h>
17*4882a593Smuzhiyun #include <linux/soc/samsung/s3c-pm.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* This array should be sorted in ascending order of the frequencies */
20*4882a593Smuzhiyun static struct cpufreq_frequency_table s3c2440_plls_12[] = {
21*4882a593Smuzhiyun { .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
22*4882a593Smuzhiyun { .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
23*4882a593Smuzhiyun { .frequency = 90000000, .driver_data = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
24*4882a593Smuzhiyun { .frequency = 100000000, .driver_data = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
25*4882a593Smuzhiyun { .frequency = 110000000, .driver_data = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
26*4882a593Smuzhiyun { .frequency = 120000000, .driver_data = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
27*4882a593Smuzhiyun { .frequency = 150000000, .driver_data = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
28*4882a593Smuzhiyun { .frequency = 160000000, .driver_data = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
29*4882a593Smuzhiyun { .frequency = 170000000, .driver_data = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
30*4882a593Smuzhiyun { .frequency = 180000000, .driver_data = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
31*4882a593Smuzhiyun { .frequency = 190000000, .driver_data = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */
32*4882a593Smuzhiyun { .frequency = 200000000, .driver_data = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */
33*4882a593Smuzhiyun { .frequency = 210000000, .driver_data = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */
34*4882a593Smuzhiyun { .frequency = 220000000, .driver_data = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */
35*4882a593Smuzhiyun { .frequency = 230000000, .driver_data = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */
36*4882a593Smuzhiyun { .frequency = 240000000, .driver_data = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */
37*4882a593Smuzhiyun { .frequency = 300000000, .driver_data = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */
38*4882a593Smuzhiyun { .frequency = 310000000, .driver_data = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */
39*4882a593Smuzhiyun { .frequency = 320000000, .driver_data = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */
40*4882a593Smuzhiyun { .frequency = 330000000, .driver_data = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */
41*4882a593Smuzhiyun { .frequency = 340000000, .driver_data = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */
42*4882a593Smuzhiyun { .frequency = 350000000, .driver_data = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */
43*4882a593Smuzhiyun { .frequency = 360000000, .driver_data = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */
44*4882a593Smuzhiyun { .frequency = 370000000, .driver_data = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */
45*4882a593Smuzhiyun { .frequency = 380000000, .driver_data = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */
46*4882a593Smuzhiyun { .frequency = 390000000, .driver_data = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */
47*4882a593Smuzhiyun { .frequency = 400000000, .driver_data = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
s3c2440_plls12_add(struct device * dev,struct subsys_interface * sif)50*4882a593Smuzhiyun static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct clk *xtal_clk;
53*4882a593Smuzhiyun unsigned long xtal;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun xtal_clk = clk_get(NULL, "xtal");
56*4882a593Smuzhiyun if (IS_ERR(xtal_clk))
57*4882a593Smuzhiyun return PTR_ERR(xtal_clk);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun xtal = clk_get_rate(xtal_clk);
60*4882a593Smuzhiyun clk_put(xtal_clk);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (xtal == 12000000) {
63*4882a593Smuzhiyun printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
64*4882a593Smuzhiyun return s3c_plltab_register(s3c2440_plls_12,
65*4882a593Smuzhiyun ARRAY_SIZE(s3c2440_plls_12));
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static struct subsys_interface s3c2440_plls12_interface = {
72*4882a593Smuzhiyun .name = "s3c2440_plls12",
73*4882a593Smuzhiyun .subsys = &s3c2440_subsys,
74*4882a593Smuzhiyun .add_dev = s3c2440_plls12_add,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
s3c2440_pll_12mhz(void)77*4882a593Smuzhiyun static int __init s3c2440_pll_12mhz(void)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun return subsys_interface_register(&s3c2440_plls12_interface);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun arch_initcall(s3c2440_pll_12mhz);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static struct subsys_interface s3c2442_plls12_interface = {
85*4882a593Smuzhiyun .name = "s3c2442_plls12",
86*4882a593Smuzhiyun .subsys = &s3c2442_subsys,
87*4882a593Smuzhiyun .add_dev = s3c2440_plls12_add,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
s3c2442_pll_12mhz(void)90*4882a593Smuzhiyun static int __init s3c2442_pll_12mhz(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun return subsys_interface_register(&s3c2442_plls12_interface);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun arch_initcall(s3c2442_pll_12mhz);
96