1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2006-2007 Simtec Electronics
4*4882a593Smuzhiyun // http://armlinux.simtec.co.uk/
5*4882a593Smuzhiyun // Ben Dooks <ben@simtec.co.uk>
6*4882a593Smuzhiyun // Vincent Sanders <vince@arm.linux.org.uk>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // S3C2410 CPU PLL tables
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/list.h>
15*4882a593Smuzhiyun #include <linux/clk.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/soc/samsung/s3c-cpufreq-core.h>
19*4882a593Smuzhiyun #include <linux/soc/samsung/s3c-pm.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* This array should be sorted in ascending order of the frequencies */
22*4882a593Smuzhiyun static struct cpufreq_frequency_table pll_vals_12MHz[] = {
23*4882a593Smuzhiyun { .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), },
24*4882a593Smuzhiyun { .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), },
25*4882a593Smuzhiyun { .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), },
26*4882a593Smuzhiyun { .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), },
27*4882a593Smuzhiyun { .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), },
28*4882a593Smuzhiyun { .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), },
29*4882a593Smuzhiyun { .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), },
30*4882a593Smuzhiyun { .frequency = 85000000, .driver_data = PLLVAL(105, 2, 2), },
31*4882a593Smuzhiyun { .frequency = 90000000, .driver_data = PLLVAL(112, 2, 2), },
32*4882a593Smuzhiyun { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2), },
33*4882a593Smuzhiyun { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2), },
34*4882a593Smuzhiyun { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2), },
35*4882a593Smuzhiyun { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2), },
36*4882a593Smuzhiyun { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1), },
37*4882a593Smuzhiyun { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1), },
38*4882a593Smuzhiyun { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1), },
39*4882a593Smuzhiyun { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1), },
40*4882a593Smuzhiyun { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1), },
41*4882a593Smuzhiyun { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1), },
42*4882a593Smuzhiyun { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1), },
43*4882a593Smuzhiyun { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1), },
44*4882a593Smuzhiyun { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1), },
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* 2410A extras */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1), },
49*4882a593Smuzhiyun { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1), },
50*4882a593Smuzhiyun { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1), },
51*4882a593Smuzhiyun { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1), },
52*4882a593Smuzhiyun { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1), },
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
s3c2410_plls_add(struct device * dev,struct subsys_interface * sif)55*4882a593Smuzhiyun static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static struct subsys_interface s3c2410_plls_interface = {
61*4882a593Smuzhiyun .name = "s3c2410_plls",
62*4882a593Smuzhiyun .subsys = &s3c2410_subsys,
63*4882a593Smuzhiyun .add_dev = s3c2410_plls_add,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
s3c2410_pll_init(void)66*4882a593Smuzhiyun static int __init s3c2410_pll_init(void)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun return subsys_interface_register(&s3c2410_plls_interface);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun arch_initcall(s3c2410_pll_init);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static struct subsys_interface s3c2410a_plls_interface = {
74*4882a593Smuzhiyun .name = "s3c2410a_plls",
75*4882a593Smuzhiyun .subsys = &s3c2410a_subsys,
76*4882a593Smuzhiyun .add_dev = s3c2410_plls_add,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
s3c2410a_pll_init(void)79*4882a593Smuzhiyun static int __init s3c2410a_pll_init(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun return subsys_interface_register(&s3c2410a_plls_interface);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun arch_initcall(s3c2410a_pll_init);
84