1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2005 Simtec Electronics 4*4882a593Smuzhiyun * http://www.simtec.co.uk/products/ 5*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * OSIRIS - CPLD control constants 8*4882a593Smuzhiyun * OSIRIS - Memory map definitions 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __MACH_S3C24XX_OSIRIS_H 12*4882a593Smuzhiyun #define __MACH_S3C24XX_OSIRIS_H __FILE__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* CTRL0 - NAND WP control */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define OSIRIS_CTRL0_NANDSEL (0x3) 17*4882a593Smuzhiyun #define OSIRIS_CTRL0_BOOT_INT (1<<3) 18*4882a593Smuzhiyun #define OSIRIS_CTRL0_PCMCIA (1<<4) 19*4882a593Smuzhiyun #define OSIRIS_CTRL0_FIX8 (1<<5) 20*4882a593Smuzhiyun #define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) 21*4882a593Smuzhiyun #define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define OSIRIS_CTRL1_FIX8 (1<<0) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define OSIRIS_ID_REVMASK (0x7) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* start peripherals off after the S3C2410 */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000)) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26)) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* we put the CPLD registers next, to get them out of the way */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000) 36*4882a593Smuzhiyun #define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000) 39*4882a593Smuzhiyun #define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23)) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000) 42*4882a593Smuzhiyun #define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23)) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000) 45*4882a593Smuzhiyun #define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000) 48*4882a593Smuzhiyun #define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23)) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* __MACH_S3C24XX_OSIRIS_H */ 51