1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2008 Openmoko, Inc. 4*4882a593Smuzhiyun * Copyright 2008 Simtec Electronics 5*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 6*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * S3C64XX - Memory map definitions 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASM_ARCH_MAP_H 12*4882a593Smuzhiyun #define __ASM_ARCH_MAP_H __FILE__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <mach/map-base.h> 15*4882a593Smuzhiyun #include "map-s3c.h" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Post-mux Chip Select Regions Xm0CSn_ 19*4882a593Smuzhiyun * These may be used by SROM, NAND or CF depending on settings 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define S3C64XX_PA_XM0CSN0 (0x10000000) 23*4882a593Smuzhiyun #define S3C64XX_PA_XM0CSN1 (0x18000000) 24*4882a593Smuzhiyun #define S3C64XX_PA_XM0CSN2 (0x20000000) 25*4882a593Smuzhiyun #define S3C64XX_PA_XM0CSN3 (0x28000000) 26*4882a593Smuzhiyun #define S3C64XX_PA_XM0CSN4 (0x30000000) 27*4882a593Smuzhiyun #define S3C64XX_PA_XM0CSN5 (0x38000000) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* HSMMC units */ 30*4882a593Smuzhiyun #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) 31*4882a593Smuzhiyun #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) 32*4882a593Smuzhiyun #define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1) 33*4882a593Smuzhiyun #define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define S3C_PA_UART (0x7F005000) 36*4882a593Smuzhiyun #define S3C_PA_UART0 (S3C_PA_UART + 0x00) 37*4882a593Smuzhiyun #define S3C_PA_UART1 (S3C_PA_UART + 0x400) 38*4882a593Smuzhiyun #define S3C_PA_UART2 (S3C_PA_UART + 0x800) 39*4882a593Smuzhiyun #define S3C_PA_UART3 (S3C_PA_UART + 0xC00) 40*4882a593Smuzhiyun #define S3C_UART_OFFSET (0x400) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* See notes on UART VA mapping in debug-macro.S */ 43*4882a593Smuzhiyun #define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define S3C_VA_UART0 S3C_VA_UARTx(0) 46*4882a593Smuzhiyun #define S3C_VA_UART1 S3C_VA_UARTx(1) 47*4882a593Smuzhiyun #define S3C_VA_UART2 S3C_VA_UARTx(2) 48*4882a593Smuzhiyun #define S3C_VA_UART3 S3C_VA_UARTx(3) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define S3C64XX_PA_SROM (0x70000000) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define S3C64XX_PA_ONENAND0 (0x70100000) 53*4882a593Smuzhiyun #define S3C64XX_PA_ONENAND0_BUF (0x20000000) 54*4882a593Smuzhiyun #define S3C64XX_SZ_ONENAND0_BUF (SZ_64M) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* NAND and OneNAND1 controllers occupy the same register region 57*4882a593Smuzhiyun (depending on SoC POP version) */ 58*4882a593Smuzhiyun #define S3C64XX_PA_ONENAND1 (0x70200000) 59*4882a593Smuzhiyun #define S3C64XX_PA_ONENAND1_BUF (0x28000000) 60*4882a593Smuzhiyun #define S3C64XX_SZ_ONENAND1_BUF (SZ_64M) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define S3C64XX_PA_NAND (0x70200000) 63*4882a593Smuzhiyun #define S3C64XX_PA_FB (0x77100000) 64*4882a593Smuzhiyun #define S3C64XX_PA_USB_HSOTG (0x7C000000) 65*4882a593Smuzhiyun #define S3C64XX_PA_WATCHDOG (0x7E004000) 66*4882a593Smuzhiyun #define S3C64XX_PA_RTC (0x7E005000) 67*4882a593Smuzhiyun #define S3C64XX_PA_KEYPAD (0x7E00A000) 68*4882a593Smuzhiyun #define S3C64XX_PA_ADC (0x7E00B000) 69*4882a593Smuzhiyun #define S3C64XX_PA_SYSCON (0x7E00F000) 70*4882a593Smuzhiyun #define S3C64XX_PA_AC97 (0x7F001000) 71*4882a593Smuzhiyun #define S3C64XX_PA_IIS0 (0x7F002000) 72*4882a593Smuzhiyun #define S3C64XX_PA_IIS1 (0x7F003000) 73*4882a593Smuzhiyun #define S3C64XX_PA_TIMER (0x7F006000) 74*4882a593Smuzhiyun #define S3C64XX_PA_IIC0 (0x7F004000) 75*4882a593Smuzhiyun #define S3C64XX_PA_SPI0 (0x7F00B000) 76*4882a593Smuzhiyun #define S3C64XX_PA_SPI1 (0x7F00C000) 77*4882a593Smuzhiyun #define S3C64XX_PA_PCM0 (0x7F009000) 78*4882a593Smuzhiyun #define S3C64XX_PA_PCM1 (0x7F00A000) 79*4882a593Smuzhiyun #define S3C64XX_PA_IISV4 (0x7F00D000) 80*4882a593Smuzhiyun #define S3C64XX_PA_IIC1 (0x7F00F000) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define S3C64XX_PA_GPIO (0x7F008000) 83*4882a593Smuzhiyun #define S3C64XX_SZ_GPIO SZ_4K 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define S3C64XX_PA_SDRAM (0x50000000) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define S3C64XX_PA_CFCON (0x70300000) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define S3C64XX_PA_VIC0 (0x71200000) 90*4882a593Smuzhiyun #define S3C64XX_PA_VIC1 (0x71300000) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define S3C64XX_PA_MODEM (0x74108000) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define S3C64XX_PA_USBHOST (0x74300000) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define S3C64XX_PA_USB_HSPHY (0x7C100000) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* compatibility defines. */ 99*4882a593Smuzhiyun #define S3C_PA_TIMER S3C64XX_PA_TIMER 100*4882a593Smuzhiyun #define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0 101*4882a593Smuzhiyun #define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1 102*4882a593Smuzhiyun #define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 103*4882a593Smuzhiyun #define S3C_PA_IIC S3C64XX_PA_IIC0 104*4882a593Smuzhiyun #define S3C_PA_IIC1 S3C64XX_PA_IIC1 105*4882a593Smuzhiyun #define S3C_PA_NAND S3C64XX_PA_NAND 106*4882a593Smuzhiyun #define S3C_PA_ONENAND S3C64XX_PA_ONENAND0 107*4882a593Smuzhiyun #define S3C_PA_ONENAND_BUF S3C64XX_PA_ONENAND0_BUF 108*4882a593Smuzhiyun #define S3C_SZ_ONENAND_BUF S3C64XX_SZ_ONENAND0_BUF 109*4882a593Smuzhiyun #define S3C_PA_FB S3C64XX_PA_FB 110*4882a593Smuzhiyun #define S3C_PA_USBHOST S3C64XX_PA_USBHOST 111*4882a593Smuzhiyun #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG 112*4882a593Smuzhiyun #define S3C_PA_RTC S3C64XX_PA_RTC 113*4882a593Smuzhiyun #define S3C_PA_WDT S3C64XX_PA_WATCHDOG 114*4882a593Smuzhiyun #define S3C_PA_SPI0 S3C64XX_PA_SPI0 115*4882a593Smuzhiyun #define S3C_PA_SPI1 S3C64XX_PA_SPI1 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define SAMSUNG_PA_ADC S3C64XX_PA_ADC 118*4882a593Smuzhiyun #define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON 119*4882a593Smuzhiyun #define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD 120*4882a593Smuzhiyun #define SAMSUNG_PA_TIMER S3C64XX_PA_TIMER 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #endif /* __ASM_ARCH_6400_MAP_H */ 123