1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2003 Simtec Electronics 4*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * S3C2410 - Memory map definitions 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_MAP_H 10*4882a593Smuzhiyun #define __ASM_ARCH_MAP_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <mach/map-base.h> 13*4882a593Smuzhiyun #include "map-s3c.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * interrupt controller is the first thing we put in, to make 17*4882a593Smuzhiyun * the assembly code for the irq detection easier 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define S3C2410_PA_IRQ (0x4A000000) 20*4882a593Smuzhiyun #define S3C24XX_SZ_IRQ SZ_1M 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* memory controller registers */ 23*4882a593Smuzhiyun #define S3C2410_PA_MEMCTRL (0x48000000) 24*4882a593Smuzhiyun #define S3C24XX_SZ_MEMCTRL SZ_1M 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Timers */ 27*4882a593Smuzhiyun #define S3C2410_PA_TIMER (0x51000000) 28*4882a593Smuzhiyun #define S3C24XX_SZ_TIMER SZ_1M 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Clock and Power management */ 31*4882a593Smuzhiyun #define S3C24XX_SZ_CLKPWR SZ_1M 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* USB Device port */ 34*4882a593Smuzhiyun #define S3C2410_PA_USBDEV (0x52000000) 35*4882a593Smuzhiyun #define S3C24XX_SZ_USBDEV SZ_1M 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Watchdog */ 38*4882a593Smuzhiyun #define S3C2410_PA_WATCHDOG (0x53000000) 39*4882a593Smuzhiyun #define S3C24XX_SZ_WATCHDOG SZ_1M 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Standard size definitions for peripheral blocks. */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define S3C24XX_SZ_UART SZ_1M 44*4882a593Smuzhiyun #define S3C24XX_SZ_IIS SZ_1M 45*4882a593Smuzhiyun #define S3C24XX_SZ_ADC SZ_1M 46*4882a593Smuzhiyun #define S3C24XX_SZ_SPI SZ_1M 47*4882a593Smuzhiyun #define S3C24XX_SZ_SDI SZ_1M 48*4882a593Smuzhiyun #define S3C24XX_SZ_NAND SZ_1M 49*4882a593Smuzhiyun #define S3C24XX_SZ_GPIO SZ_1M 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* USB host controller */ 52*4882a593Smuzhiyun #define S3C2410_PA_USBHOST (0x49000000) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */ 55*4882a593Smuzhiyun #define S3C2416_PA_HSUDC (0x49800000) 56*4882a593Smuzhiyun #define S3C2416_SZ_HSUDC (SZ_4K) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* DMA controller */ 59*4882a593Smuzhiyun #define S3C2410_PA_DMA (0x4B000000) 60*4882a593Smuzhiyun #define S3C24XX_SZ_DMA SZ_1M 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Clock and Power management */ 63*4882a593Smuzhiyun #define S3C2410_PA_CLKPWR (0x4C000000) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* LCD controller */ 66*4882a593Smuzhiyun #define S3C2410_PA_LCD (0x4D000000) 67*4882a593Smuzhiyun #define S3C24XX_SZ_LCD SZ_1M 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* NAND flash controller */ 70*4882a593Smuzhiyun #define S3C2410_PA_NAND (0x4E000000) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* IIC hardware controller */ 73*4882a593Smuzhiyun #define S3C2410_PA_IIC (0x54000000) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* IIS controller */ 76*4882a593Smuzhiyun #define S3C2410_PA_IIS (0x55000000) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* RTC */ 79*4882a593Smuzhiyun #define S3C2410_PA_RTC (0x57000000) 80*4882a593Smuzhiyun #define S3C24XX_SZ_RTC SZ_1M 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* ADC */ 83*4882a593Smuzhiyun #define S3C2410_PA_ADC (0x58000000) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* SPI */ 86*4882a593Smuzhiyun #define S3C2410_PA_SPI (0x59000000) 87*4882a593Smuzhiyun #define S3C2443_PA_SPI0 (0x52000000) 88*4882a593Smuzhiyun #define S3C2443_PA_SPI1 S3C2410_PA_SPI 89*4882a593Smuzhiyun #define S3C2410_SPI1 (0x20) 90*4882a593Smuzhiyun #define S3C2412_SPI1 (0x100) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* SDI */ 93*4882a593Smuzhiyun #define S3C2410_PA_SDI (0x5A000000) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* CAMIF */ 96*4882a593Smuzhiyun #define S3C2440_PA_CAMIF (0x4F000000) 97*4882a593Smuzhiyun #define S3C2440_SZ_CAMIF SZ_1M 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* AC97 */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define S3C2440_PA_AC97 (0x5B000000) 102*4882a593Smuzhiyun #define S3C2440_SZ_AC97 SZ_1M 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* S3C2443/S3C2416 High-speed SD/MMC */ 105*4882a593Smuzhiyun #define S3C2443_PA_HSMMC (0x4A800000) 106*4882a593Smuzhiyun #define S3C2416_PA_HSMMC0 (0x4AC00000) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define S3C2443_PA_FB (0x4C800000) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* S3C2412 memory and IO controls */ 111*4882a593Smuzhiyun #define S3C2412_PA_SSMC (0x4F000000) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define S3C2412_PA_EBI (0x48800000) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* physical addresses of all the chip-select areas */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define S3C2410_CS0 (0x00000000) 118*4882a593Smuzhiyun #define S3C2410_CS1 (0x08000000) 119*4882a593Smuzhiyun #define S3C2410_CS2 (0x10000000) 120*4882a593Smuzhiyun #define S3C2410_CS3 (0x18000000) 121*4882a593Smuzhiyun #define S3C2410_CS4 (0x20000000) 122*4882a593Smuzhiyun #define S3C2410_CS5 (0x28000000) 123*4882a593Smuzhiyun #define S3C2410_CS6 (0x30000000) 124*4882a593Smuzhiyun #define S3C2410_CS7 (0x38000000) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define S3C2410_SDRAM_PA (S3C2410_CS6) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* Use a single interface for common resources between S3C24XX cpus */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define S3C24XX_PA_IRQ S3C2410_PA_IRQ 131*4882a593Smuzhiyun #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL 132*4882a593Smuzhiyun #define S3C24XX_PA_DMA S3C2410_PA_DMA 133*4882a593Smuzhiyun #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR 134*4882a593Smuzhiyun #define S3C24XX_PA_LCD S3C2410_PA_LCD 135*4882a593Smuzhiyun #define S3C24XX_PA_TIMER S3C2410_PA_TIMER 136*4882a593Smuzhiyun #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV 137*4882a593Smuzhiyun #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG 138*4882a593Smuzhiyun #define S3C24XX_PA_IIS S3C2410_PA_IIS 139*4882a593Smuzhiyun #define S3C24XX_PA_RTC S3C2410_PA_RTC 140*4882a593Smuzhiyun #define S3C24XX_PA_ADC S3C2410_PA_ADC 141*4882a593Smuzhiyun #define S3C24XX_PA_SPI S3C2410_PA_SPI 142*4882a593Smuzhiyun #define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1) 143*4882a593Smuzhiyun #define S3C24XX_PA_SDI S3C2410_PA_SDI 144*4882a593Smuzhiyun #define S3C24XX_PA_NAND S3C2410_PA_NAND 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define S3C_PA_FB S3C2443_PA_FB 147*4882a593Smuzhiyun #define S3C_PA_IIC S3C2410_PA_IIC 148*4882a593Smuzhiyun #define S3C_PA_USBHOST S3C2410_PA_USBHOST 149*4882a593Smuzhiyun #define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0 150*4882a593Smuzhiyun #define S3C_PA_HSMMC1 S3C2443_PA_HSMMC 151*4882a593Smuzhiyun #define S3C_PA_WDT S3C2410_PA_WATCHDOG 152*4882a593Smuzhiyun #define S3C_PA_NAND S3C24XX_PA_NAND 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define S3C_PA_SPI0 S3C2443_PA_SPI0 155*4882a593Smuzhiyun #define S3C_PA_SPI1 S3C2443_PA_SPI1 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define SAMSUNG_PA_TIMER S3C2410_PA_TIMER 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #endif /* __ASM_ARCH_MAP_H */ 160