1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2008 Simtec Electronics 4*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * S3C24XX - Memory map definitions 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_PLAT_MAP_S3C_H 10*4882a593Smuzhiyun #define __ASM_PLAT_MAP_S3C_H __FILE__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "map.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define S3C24XX_VA_IRQ S3C_VA_IRQ 15*4882a593Smuzhiyun #define S3C24XX_VA_MEMCTRL S3C_VA_MEM 16*4882a593Smuzhiyun #define S3C24XX_VA_UART S3C_VA_UART 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define S3C24XX_VA_TIMER S3C_VA_TIMER 19*4882a593Smuzhiyun #define S3C24XX_VA_CLKPWR S3C_VA_SYS 20*4882a593Smuzhiyun #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) 23*4882a593Smuzhiyun #define S3C2412_VA_EBI S3C_ADDR_CPU(0x00100000) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define S3C2410_PA_UART (0x50000000) 26*4882a593Smuzhiyun #define S3C24XX_PA_UART S3C2410_PA_UART 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * GPIO ports 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * the calculation for the VA of this must ensure that 32*4882a593Smuzhiyun * it is the same distance apart from the UART in the 33*4882a593Smuzhiyun * phsyical address space, as the initial mapping for the IO 34*4882a593Smuzhiyun * is done as a 1:1 mapping. This puts it (currently) at 35*4882a593Smuzhiyun * 0xFA800000, which is not in the way of any current mapping 36*4882a593Smuzhiyun * by the base system. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define S3C2410_PA_GPIO (0x56000000) 40*4882a593Smuzhiyun #define S3C24XX_PA_GPIO S3C2410_PA_GPIO 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) 43*4882a593Smuzhiyun #define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000) 46*4882a593Smuzhiyun #define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define S3C2410_ADDR(x) S3C_ADDR(x) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* deal with the registers that move under the 2412/2413 */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #if defined(CONFIG_CPU_S3C2412) 55*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 56*4882a593Smuzhiyun extern void __iomem *s3c24xx_va_gpio2; 57*4882a593Smuzhiyun #endif 58*4882a593Smuzhiyun #ifdef CONFIG_CPU_S3C2412_ONLY 59*4882a593Smuzhiyun #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) 60*4882a593Smuzhiyun #else 61*4882a593Smuzhiyun #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 62*4882a593Smuzhiyun #endif 63*4882a593Smuzhiyun #else 64*4882a593Smuzhiyun #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO 65*4882a593Smuzhiyun #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO 66*4882a593Smuzhiyun #endif 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #include "map-s5p.h" 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* __ASM_PLAT_MAP_S3C_H */ 71