xref: /OK3568_Linux_fs/kernel/arch/arm/mach-s3c/mach-crag6410.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright 2011 Wolfson Microelectronics plc
4*4882a593Smuzhiyun //	Mark Brown <broonie@opensource.wolfsonmicro.com>
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // Copyright 2011 Simtec Electronics
7*4882a593Smuzhiyun //	Ben Dooks <ben@simtec.co.uk>
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/list.h>
11*4882a593Smuzhiyun #include <linux/serial_core.h>
12*4882a593Smuzhiyun #include <linux/serial_s3c.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/fb.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/gpio.h>
18*4882a593Smuzhiyun #include <linux/gpio/machine.h>
19*4882a593Smuzhiyun #include <linux/leds.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <linux/mmc/host.h>
22*4882a593Smuzhiyun #include <linux/regulator/machine.h>
23*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
24*4882a593Smuzhiyun #include <linux/pwm.h>
25*4882a593Smuzhiyun #include <linux/pwm_backlight.h>
26*4882a593Smuzhiyun #include <linux/dm9000.h>
27*4882a593Smuzhiyun #include <linux/gpio_keys.h>
28*4882a593Smuzhiyun #include <linux/gpio/driver.h>
29*4882a593Smuzhiyun #include <linux/spi/spi.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <linux/platform_data/pca953x.h>
32*4882a593Smuzhiyun #include <linux/platform_data/s3c-hsotg.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #include <video/platform_lcd.h>
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #include <linux/mfd/wm831x/core.h>
37*4882a593Smuzhiyun #include <linux/mfd/wm831x/pdata.h>
38*4882a593Smuzhiyun #include <linux/mfd/wm831x/irq.h>
39*4882a593Smuzhiyun #include <linux/mfd/wm831x/gpio.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #include <sound/wm1250-ev1.h>
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #include <asm/mach/arch.h>
44*4882a593Smuzhiyun #include <asm/mach-types.h>
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #include <video/samsung_fimd.h>
47*4882a593Smuzhiyun #include "map.h"
48*4882a593Smuzhiyun #include "regs-gpio.h"
49*4882a593Smuzhiyun #include "gpio-samsung.h"
50*4882a593Smuzhiyun #include <mach/irqs.h>
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #include "fb.h"
53*4882a593Smuzhiyun #include "sdhci.h"
54*4882a593Smuzhiyun #include "gpio-cfg.h"
55*4882a593Smuzhiyun #include <linux/platform_data/spi-s3c64xx.h>
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #include "keypad.h"
58*4882a593Smuzhiyun #include "devs.h"
59*4882a593Smuzhiyun #include "cpu.h"
60*4882a593Smuzhiyun #include <linux/soc/samsung/s3c-adc.h>
61*4882a593Smuzhiyun #include <linux/platform_data/i2c-s3c2410.h>
62*4882a593Smuzhiyun #include "pm.h"
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #include "s3c64xx.h"
65*4882a593Smuzhiyun #include "crag6410.h"
66*4882a593Smuzhiyun #include "regs-gpio-memport-s3c64xx.h"
67*4882a593Smuzhiyun #include "regs-modem-s3c64xx.h"
68*4882a593Smuzhiyun #include "regs-sys-s3c64xx.h"
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /* serial port setup */
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
73*4882a593Smuzhiyun #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
74*4882a593Smuzhiyun #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
77*4882a593Smuzhiyun 	[0] = {
78*4882a593Smuzhiyun 		.hwport		= 0,
79*4882a593Smuzhiyun 		.flags		= 0,
80*4882a593Smuzhiyun 		.ucon		= UCON,
81*4882a593Smuzhiyun 		.ulcon		= ULCON,
82*4882a593Smuzhiyun 		.ufcon		= UFCON,
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun 	[1] = {
85*4882a593Smuzhiyun 		.hwport		= 1,
86*4882a593Smuzhiyun 		.flags		= 0,
87*4882a593Smuzhiyun 		.ucon		= UCON,
88*4882a593Smuzhiyun 		.ulcon		= ULCON,
89*4882a593Smuzhiyun 		.ufcon		= UFCON,
90*4882a593Smuzhiyun 	},
91*4882a593Smuzhiyun 	[2] = {
92*4882a593Smuzhiyun 		.hwport		= 2,
93*4882a593Smuzhiyun 		.flags		= 0,
94*4882a593Smuzhiyun 		.ucon		= UCON,
95*4882a593Smuzhiyun 		.ulcon		= ULCON,
96*4882a593Smuzhiyun 		.ufcon		= UFCON,
97*4882a593Smuzhiyun 	},
98*4882a593Smuzhiyun 	[3] = {
99*4882a593Smuzhiyun 		.hwport		= 3,
100*4882a593Smuzhiyun 		.flags		= 0,
101*4882a593Smuzhiyun 		.ucon		= UCON,
102*4882a593Smuzhiyun 		.ulcon		= ULCON,
103*4882a593Smuzhiyun 		.ufcon		= UFCON,
104*4882a593Smuzhiyun 	},
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static struct pwm_lookup crag6410_pwm_lookup[] = {
108*4882a593Smuzhiyun 	PWM_LOOKUP("samsung-pwm", 0, "pwm-backlight", NULL, 100000,
109*4882a593Smuzhiyun 		   PWM_POLARITY_NORMAL),
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun static struct platform_pwm_backlight_data crag6410_backlight_data = {
113*4882a593Smuzhiyun 	.max_brightness	= 1000,
114*4882a593Smuzhiyun 	.dft_brightness	= 600,
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun static struct platform_device crag6410_backlight_device = {
118*4882a593Smuzhiyun 	.name		= "pwm-backlight",
119*4882a593Smuzhiyun 	.id		= -1,
120*4882a593Smuzhiyun 	.dev		= {
121*4882a593Smuzhiyun 		.parent	= &samsung_device_pwm.dev,
122*4882a593Smuzhiyun 		.platform_data = &crag6410_backlight_data,
123*4882a593Smuzhiyun 	},
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
crag6410_lcd_power_set(struct plat_lcd_data * pd,unsigned int power)126*4882a593Smuzhiyun static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	pr_debug("%s: setting power %d\n", __func__, power);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	if (power) {
131*4882a593Smuzhiyun 		gpio_set_value(S3C64XX_GPB(0), 1);
132*4882a593Smuzhiyun 		msleep(1);
133*4882a593Smuzhiyun 		s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
134*4882a593Smuzhiyun 	} else {
135*4882a593Smuzhiyun 		gpio_direction_output(S3C64XX_GPF(14), 0);
136*4882a593Smuzhiyun 		gpio_set_value(S3C64XX_GPB(0), 0);
137*4882a593Smuzhiyun 	}
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun static struct platform_device crag6410_lcd_powerdev = {
141*4882a593Smuzhiyun 	.name			= "platform-lcd",
142*4882a593Smuzhiyun 	.id			= -1,
143*4882a593Smuzhiyun 	.dev.parent		= &s3c_device_fb.dev,
144*4882a593Smuzhiyun 	.dev.platform_data	= &(struct plat_lcd_data) {
145*4882a593Smuzhiyun 		.set_power	= crag6410_lcd_power_set,
146*4882a593Smuzhiyun 	},
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun /* 640x480 URT */
150*4882a593Smuzhiyun static struct s3c_fb_pd_win crag6410_fb_win0 = {
151*4882a593Smuzhiyun 	.max_bpp	= 32,
152*4882a593Smuzhiyun 	.default_bpp	= 16,
153*4882a593Smuzhiyun 	.xres		= 640,
154*4882a593Smuzhiyun 	.yres		= 480,
155*4882a593Smuzhiyun 	.virtual_y	= 480 * 2,
156*4882a593Smuzhiyun 	.virtual_x	= 640,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static struct fb_videomode crag6410_lcd_timing = {
160*4882a593Smuzhiyun 	.left_margin	= 150,
161*4882a593Smuzhiyun 	.right_margin	= 80,
162*4882a593Smuzhiyun 	.upper_margin	= 40,
163*4882a593Smuzhiyun 	.lower_margin	= 5,
164*4882a593Smuzhiyun 	.hsync_len	= 40,
165*4882a593Smuzhiyun 	.vsync_len	= 5,
166*4882a593Smuzhiyun 	.xres		= 640,
167*4882a593Smuzhiyun 	.yres		= 480,
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
171*4882a593Smuzhiyun static struct s3c_fb_platdata crag6410_lcd_pdata = {
172*4882a593Smuzhiyun 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
173*4882a593Smuzhiyun 	.vtiming	= &crag6410_lcd_timing,
174*4882a593Smuzhiyun 	.win[0]		= &crag6410_fb_win0,
175*4882a593Smuzhiyun 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
176*4882a593Smuzhiyun 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun /* 2x6 keypad */
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun static uint32_t crag6410_keymap[] = {
182*4882a593Smuzhiyun 	/* KEY(row, col, keycode) */
183*4882a593Smuzhiyun 	KEY(0, 0, KEY_VOLUMEUP),
184*4882a593Smuzhiyun 	KEY(0, 1, KEY_HOME),
185*4882a593Smuzhiyun 	KEY(0, 2, KEY_VOLUMEDOWN),
186*4882a593Smuzhiyun 	KEY(0, 3, KEY_HELP),
187*4882a593Smuzhiyun 	KEY(0, 4, KEY_MENU),
188*4882a593Smuzhiyun 	KEY(0, 5, KEY_MEDIA),
189*4882a593Smuzhiyun 	KEY(1, 0, 232),
190*4882a593Smuzhiyun 	KEY(1, 1, KEY_DOWN),
191*4882a593Smuzhiyun 	KEY(1, 2, KEY_LEFT),
192*4882a593Smuzhiyun 	KEY(1, 3, KEY_UP),
193*4882a593Smuzhiyun 	KEY(1, 4, KEY_RIGHT),
194*4882a593Smuzhiyun 	KEY(1, 5, KEY_CAMERA),
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun static struct matrix_keymap_data crag6410_keymap_data = {
198*4882a593Smuzhiyun 	.keymap		= crag6410_keymap,
199*4882a593Smuzhiyun 	.keymap_size	= ARRAY_SIZE(crag6410_keymap),
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static struct samsung_keypad_platdata crag6410_keypad_data = {
203*4882a593Smuzhiyun 	.keymap_data	= &crag6410_keymap_data,
204*4882a593Smuzhiyun 	.rows		= 2,
205*4882a593Smuzhiyun 	.cols		= 6,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static struct gpio_keys_button crag6410_gpio_keys[] = {
209*4882a593Smuzhiyun 	[0] = {
210*4882a593Smuzhiyun 		.code	= KEY_SUSPEND,
211*4882a593Smuzhiyun 		.gpio	= S3C64XX_GPL(10),	/* EINT 18 */
212*4882a593Smuzhiyun 		.type	= EV_KEY,
213*4882a593Smuzhiyun 		.wakeup	= 1,
214*4882a593Smuzhiyun 		.active_low = 1,
215*4882a593Smuzhiyun 	},
216*4882a593Smuzhiyun 	[1] = {
217*4882a593Smuzhiyun 		.code	= SW_FRONT_PROXIMITY,
218*4882a593Smuzhiyun 		.gpio	= S3C64XX_GPN(11),	/* EINT 11 */
219*4882a593Smuzhiyun 		.type	= EV_SW,
220*4882a593Smuzhiyun 	},
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun static struct gpio_keys_platform_data crag6410_gpio_keydata = {
224*4882a593Smuzhiyun 	.buttons	= crag6410_gpio_keys,
225*4882a593Smuzhiyun 	.nbuttons	= ARRAY_SIZE(crag6410_gpio_keys),
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun static struct platform_device crag6410_gpio_keydev = {
229*4882a593Smuzhiyun 	.name		= "gpio-keys",
230*4882a593Smuzhiyun 	.id		= 0,
231*4882a593Smuzhiyun 	.dev.platform_data = &crag6410_gpio_keydata,
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun static struct resource crag6410_dm9k_resource[] = {
235*4882a593Smuzhiyun 	[0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5, 2),
236*4882a593Smuzhiyun 	[1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5 + (1 << 8), 2),
237*4882a593Smuzhiyun 	[2] = DEFINE_RES_NAMED(S3C_EINT(17), 1, NULL, IORESOURCE_IRQ \
238*4882a593Smuzhiyun 				| IORESOURCE_IRQ_HIGHLEVEL),
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun static struct dm9000_plat_data mini6410_dm9k_pdata = {
242*4882a593Smuzhiyun 	.flags	= DM9000_PLATF_16BITONLY,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun static struct platform_device crag6410_dm9k_device = {
246*4882a593Smuzhiyun 	.name		= "dm9000",
247*4882a593Smuzhiyun 	.id		= -1,
248*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(crag6410_dm9k_resource),
249*4882a593Smuzhiyun 	.resource	= crag6410_dm9k_resource,
250*4882a593Smuzhiyun 	.dev.platform_data = &mini6410_dm9k_pdata,
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun static struct resource crag6410_mmgpio_resource[] = {
254*4882a593Smuzhiyun 	[0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"),
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun static struct platform_device crag6410_mmgpio = {
258*4882a593Smuzhiyun 	.name		= "basic-mmio-gpio",
259*4882a593Smuzhiyun 	.id		= -1,
260*4882a593Smuzhiyun 	.resource	= crag6410_mmgpio_resource,
261*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(crag6410_mmgpio_resource),
262*4882a593Smuzhiyun 	.dev.platform_data = &(struct bgpio_pdata) {
263*4882a593Smuzhiyun 		.base	= MMGPIO_GPIO_BASE,
264*4882a593Smuzhiyun 	},
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun static struct platform_device speyside_device = {
268*4882a593Smuzhiyun 	.name		= "speyside",
269*4882a593Smuzhiyun 	.id		= -1,
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun static struct platform_device lowland_device = {
273*4882a593Smuzhiyun 	.name		= "lowland",
274*4882a593Smuzhiyun 	.id		= -1,
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun static struct platform_device tobermory_device = {
278*4882a593Smuzhiyun 	.name		= "tobermory",
279*4882a593Smuzhiyun 	.id		= -1,
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun static struct platform_device littlemill_device = {
283*4882a593Smuzhiyun 	.name		= "littlemill",
284*4882a593Smuzhiyun 	.id		= -1,
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun static struct platform_device bells_wm2200_device = {
288*4882a593Smuzhiyun 	.name		= "bells",
289*4882a593Smuzhiyun 	.id		= 0,
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static struct platform_device bells_wm5102_device = {
293*4882a593Smuzhiyun 	.name		= "bells",
294*4882a593Smuzhiyun 	.id		= 1,
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun static struct platform_device bells_wm5110_device = {
298*4882a593Smuzhiyun 	.name		= "bells",
299*4882a593Smuzhiyun 	.id		= 2,
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun static struct regulator_consumer_supply wallvdd_consumers[] = {
303*4882a593Smuzhiyun 	REGULATOR_SUPPLY("SPKVDD", "1-001a"),
304*4882a593Smuzhiyun 	REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
305*4882a593Smuzhiyun 	REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
306*4882a593Smuzhiyun 	REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
307*4882a593Smuzhiyun 	REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	REGULATOR_SUPPLY("SPKVDDL", "spi0.1"),
310*4882a593Smuzhiyun 	REGULATOR_SUPPLY("SPKVDDR", "spi0.1"),
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DC1VDD", "0-0034"),
313*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DC2VDD", "0-0034"),
314*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DC3VDD", "0-0034"),
315*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO1VDD", "0-0034"),
316*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO2VDD", "0-0034"),
317*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO4VDD", "0-0034"),
318*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO5VDD", "0-0034"),
319*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO6VDD", "0-0034"),
320*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO7VDD", "0-0034"),
321*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO8VDD", "0-0034"),
322*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO9VDD", "0-0034"),
323*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO10VDD", "0-0034"),
324*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO11VDD", "0-0034"),
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DC1VDD", "1-0034"),
327*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DC2VDD", "1-0034"),
328*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DC3VDD", "1-0034"),
329*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO1VDD", "1-0034"),
330*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO2VDD", "1-0034"),
331*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO4VDD", "1-0034"),
332*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO5VDD", "1-0034"),
333*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO6VDD", "1-0034"),
334*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO7VDD", "1-0034"),
335*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO8VDD", "1-0034"),
336*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO9VDD", "1-0034"),
337*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO10VDD", "1-0034"),
338*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDO11VDD", "1-0034"),
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun static struct regulator_init_data wallvdd_data = {
342*4882a593Smuzhiyun 	.constraints = {
343*4882a593Smuzhiyun 		.always_on = 1,
344*4882a593Smuzhiyun 	},
345*4882a593Smuzhiyun 	.num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
346*4882a593Smuzhiyun 	.consumer_supplies = wallvdd_consumers,
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun static struct fixed_voltage_config wallvdd_pdata = {
350*4882a593Smuzhiyun 	.supply_name = "WALLVDD",
351*4882a593Smuzhiyun 	.microvolts = 5000000,
352*4882a593Smuzhiyun 	.init_data = &wallvdd_data,
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static struct platform_device wallvdd_device = {
356*4882a593Smuzhiyun 	.name		= "reg-fixed-voltage",
357*4882a593Smuzhiyun 	.id		= -1,
358*4882a593Smuzhiyun 	.dev = {
359*4882a593Smuzhiyun 		.platform_data = &wallvdd_pdata,
360*4882a593Smuzhiyun 	},
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun static struct platform_device *crag6410_devices[] __initdata = {
364*4882a593Smuzhiyun 	&s3c_device_hsmmc0,
365*4882a593Smuzhiyun 	&s3c_device_hsmmc2,
366*4882a593Smuzhiyun 	&s3c_device_i2c0,
367*4882a593Smuzhiyun 	&s3c_device_i2c1,
368*4882a593Smuzhiyun 	&s3c_device_fb,
369*4882a593Smuzhiyun 	&s3c_device_ohci,
370*4882a593Smuzhiyun 	&s3c_device_usb_hsotg,
371*4882a593Smuzhiyun 	&samsung_device_pwm,
372*4882a593Smuzhiyun 	&s3c64xx_device_iis0,
373*4882a593Smuzhiyun 	&s3c64xx_device_iis1,
374*4882a593Smuzhiyun 	&samsung_device_keypad,
375*4882a593Smuzhiyun 	&crag6410_gpio_keydev,
376*4882a593Smuzhiyun 	&crag6410_dm9k_device,
377*4882a593Smuzhiyun 	&s3c64xx_device_spi0,
378*4882a593Smuzhiyun 	&crag6410_mmgpio,
379*4882a593Smuzhiyun 	&crag6410_lcd_powerdev,
380*4882a593Smuzhiyun 	&crag6410_backlight_device,
381*4882a593Smuzhiyun 	&speyside_device,
382*4882a593Smuzhiyun 	&tobermory_device,
383*4882a593Smuzhiyun 	&littlemill_device,
384*4882a593Smuzhiyun 	&lowland_device,
385*4882a593Smuzhiyun 	&bells_wm2200_device,
386*4882a593Smuzhiyun 	&bells_wm5102_device,
387*4882a593Smuzhiyun 	&bells_wm5110_device,
388*4882a593Smuzhiyun 	&wallvdd_device,
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun static struct pca953x_platform_data crag6410_pca_data = {
392*4882a593Smuzhiyun 	.gpio_base	= PCA935X_GPIO_BASE,
393*4882a593Smuzhiyun 	.irq_base	= -1,
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun /* VDDARM is controlled by DVS1 connected to GPK(0) */
397*4882a593Smuzhiyun static struct wm831x_buckv_pdata vddarm_pdata = {
398*4882a593Smuzhiyun 	.dvs_control_src = 1,
399*4882a593Smuzhiyun };
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun static struct regulator_consumer_supply vddarm_consumers[] = {
402*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vddarm", NULL),
403*4882a593Smuzhiyun };
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun static struct regulator_init_data vddarm = {
406*4882a593Smuzhiyun 	.constraints = {
407*4882a593Smuzhiyun 		.name = "VDDARM",
408*4882a593Smuzhiyun 		.min_uV = 1000000,
409*4882a593Smuzhiyun 		.max_uV = 1300000,
410*4882a593Smuzhiyun 		.always_on = 1,
411*4882a593Smuzhiyun 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
412*4882a593Smuzhiyun 	},
413*4882a593Smuzhiyun 	.num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
414*4882a593Smuzhiyun 	.consumer_supplies = vddarm_consumers,
415*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
416*4882a593Smuzhiyun 	.driver_data = &vddarm_pdata,
417*4882a593Smuzhiyun };
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun static struct regulator_consumer_supply vddint_consumers[] = {
420*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vddint", NULL),
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun static struct regulator_init_data vddint = {
424*4882a593Smuzhiyun 	.constraints = {
425*4882a593Smuzhiyun 		.name = "VDDINT",
426*4882a593Smuzhiyun 		.min_uV = 1000000,
427*4882a593Smuzhiyun 		.max_uV = 1200000,
428*4882a593Smuzhiyun 		.always_on = 1,
429*4882a593Smuzhiyun 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
430*4882a593Smuzhiyun 	},
431*4882a593Smuzhiyun 	.num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
432*4882a593Smuzhiyun 	.consumer_supplies = vddint_consumers,
433*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
434*4882a593Smuzhiyun };
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun static struct regulator_init_data vddmem = {
437*4882a593Smuzhiyun 	.constraints = {
438*4882a593Smuzhiyun 		.name = "VDDMEM",
439*4882a593Smuzhiyun 		.always_on = 1,
440*4882a593Smuzhiyun 	},
441*4882a593Smuzhiyun };
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun static struct regulator_init_data vddsys = {
444*4882a593Smuzhiyun 	.constraints = {
445*4882a593Smuzhiyun 		.name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
446*4882a593Smuzhiyun 		.always_on = 1,
447*4882a593Smuzhiyun 	},
448*4882a593Smuzhiyun };
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun static struct regulator_consumer_supply vddmmc_consumers[] = {
451*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
452*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
453*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
454*4882a593Smuzhiyun };
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun static struct regulator_init_data vddmmc = {
457*4882a593Smuzhiyun 	.constraints = {
458*4882a593Smuzhiyun 		.name = "VDDMMC,UH",
459*4882a593Smuzhiyun 		.always_on = 1,
460*4882a593Smuzhiyun 	},
461*4882a593Smuzhiyun 	.num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
462*4882a593Smuzhiyun 	.consumer_supplies = vddmmc_consumers,
463*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
464*4882a593Smuzhiyun };
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun static struct regulator_init_data vddotgi = {
467*4882a593Smuzhiyun 	.constraints = {
468*4882a593Smuzhiyun 		.name = "VDDOTGi",
469*4882a593Smuzhiyun 		.always_on = 1,
470*4882a593Smuzhiyun 	},
471*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun static struct regulator_init_data vddotg = {
475*4882a593Smuzhiyun 	.constraints = {
476*4882a593Smuzhiyun 		.name = "VDDOTG",
477*4882a593Smuzhiyun 		.always_on = 1,
478*4882a593Smuzhiyun 	},
479*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
480*4882a593Smuzhiyun };
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun static struct regulator_init_data vddhi = {
483*4882a593Smuzhiyun 	.constraints = {
484*4882a593Smuzhiyun 		.name = "VDDHI",
485*4882a593Smuzhiyun 		.always_on = 1,
486*4882a593Smuzhiyun 	},
487*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
488*4882a593Smuzhiyun };
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun static struct regulator_init_data vddadc = {
491*4882a593Smuzhiyun 	.constraints = {
492*4882a593Smuzhiyun 		.name = "VDDADC,VDDDAC",
493*4882a593Smuzhiyun 		.always_on = 1,
494*4882a593Smuzhiyun 	},
495*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun static struct regulator_init_data vddmem0 = {
499*4882a593Smuzhiyun 	.constraints = {
500*4882a593Smuzhiyun 		.name = "VDDMEM0",
501*4882a593Smuzhiyun 		.always_on = 1,
502*4882a593Smuzhiyun 	},
503*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
504*4882a593Smuzhiyun };
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun static struct regulator_init_data vddpll = {
507*4882a593Smuzhiyun 	.constraints = {
508*4882a593Smuzhiyun 		.name = "VDDPLL",
509*4882a593Smuzhiyun 		.always_on = 1,
510*4882a593Smuzhiyun 	},
511*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
512*4882a593Smuzhiyun };
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun static struct regulator_init_data vddlcd = {
515*4882a593Smuzhiyun 	.constraints = {
516*4882a593Smuzhiyun 		.name = "VDDLCD",
517*4882a593Smuzhiyun 		.always_on = 1,
518*4882a593Smuzhiyun 	},
519*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
520*4882a593Smuzhiyun };
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun static struct regulator_init_data vddalive = {
523*4882a593Smuzhiyun 	.constraints = {
524*4882a593Smuzhiyun 		.name = "VDDALIVE",
525*4882a593Smuzhiyun 		.always_on = 1,
526*4882a593Smuzhiyun 	},
527*4882a593Smuzhiyun 	.supply_regulator = "WALLVDD",
528*4882a593Smuzhiyun };
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun static struct wm831x_backup_pdata banff_backup_pdata = {
531*4882a593Smuzhiyun 	.charger_enable = 1,
532*4882a593Smuzhiyun 	.vlim = 2500,  /* mV */
533*4882a593Smuzhiyun 	.ilim = 200,   /* uA */
534*4882a593Smuzhiyun };
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun static struct wm831x_status_pdata banff_red_led = {
537*4882a593Smuzhiyun 	.name = "banff:red:",
538*4882a593Smuzhiyun 	.default_src = WM831X_STATUS_MANUAL,
539*4882a593Smuzhiyun };
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun static struct wm831x_status_pdata banff_green_led = {
542*4882a593Smuzhiyun 	.name = "banff:green:",
543*4882a593Smuzhiyun 	.default_src = WM831X_STATUS_MANUAL,
544*4882a593Smuzhiyun };
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun static struct wm831x_touch_pdata touch_pdata = {
547*4882a593Smuzhiyun 	.data_irq = S3C_EINT(26),
548*4882a593Smuzhiyun 	.pd_irq = S3C_EINT(27),
549*4882a593Smuzhiyun };
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun static struct wm831x_pdata crag_pmic_pdata = {
552*4882a593Smuzhiyun 	.wm831x_num = 1,
553*4882a593Smuzhiyun 	.irq_base = BANFF_PMIC_IRQ_BASE,
554*4882a593Smuzhiyun 	.gpio_base = BANFF_PMIC_GPIO_BASE,
555*4882a593Smuzhiyun 	.soft_shutdown = true,
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	.backup = &banff_backup_pdata,
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	.gpio_defaults = {
560*4882a593Smuzhiyun 		/* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
561*4882a593Smuzhiyun 		[4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
562*4882a593Smuzhiyun 		/* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
563*4882a593Smuzhiyun 		[10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
564*4882a593Smuzhiyun 		/* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
565*4882a593Smuzhiyun 		[11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
566*4882a593Smuzhiyun 	},
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	.dcdc = {
569*4882a593Smuzhiyun 		&vddarm,  /* DCDC1 */
570*4882a593Smuzhiyun 		&vddint,  /* DCDC2 */
571*4882a593Smuzhiyun 		&vddmem,  /* DCDC3 */
572*4882a593Smuzhiyun 	},
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 	.ldo = {
575*4882a593Smuzhiyun 		&vddsys,   /* LDO1 */
576*4882a593Smuzhiyun 		&vddmmc,   /* LDO2 */
577*4882a593Smuzhiyun 		NULL,      /* LDO3 */
578*4882a593Smuzhiyun 		&vddotgi,  /* LDO4 */
579*4882a593Smuzhiyun 		&vddotg,   /* LDO5 */
580*4882a593Smuzhiyun 		&vddhi,    /* LDO6 */
581*4882a593Smuzhiyun 		&vddadc,   /* LDO7 */
582*4882a593Smuzhiyun 		&vddmem0,  /* LDO8 */
583*4882a593Smuzhiyun 		&vddpll,   /* LDO9 */
584*4882a593Smuzhiyun 		&vddlcd,   /* LDO10 */
585*4882a593Smuzhiyun 		&vddalive, /* LDO11 */
586*4882a593Smuzhiyun 	},
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	.status = {
589*4882a593Smuzhiyun 		&banff_green_led,
590*4882a593Smuzhiyun 		&banff_red_led,
591*4882a593Smuzhiyun 	},
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	.touch = &touch_pdata,
594*4882a593Smuzhiyun };
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun /*
597*4882a593Smuzhiyun  * VDDARM is eventually ending up as a regulator hanging on the MFD cell device
598*4882a593Smuzhiyun  * "wm831x-buckv.1" spawn from drivers/mfd/wm831x-core.c.
599*4882a593Smuzhiyun  *
600*4882a593Smuzhiyun  * From the note on the platform data we can see that this is clearly DVS1
601*4882a593Smuzhiyun  * and assigned as dcdc1 resource to the MFD core which sets .id of the cell
602*4882a593Smuzhiyun  * spawning the DVS1 platform device to 1, then the cell platform device
603*4882a593Smuzhiyun  * name is calculated from 10*instance + id resulting in the device name
604*4882a593Smuzhiyun  * "wm831x-buckv.11"
605*4882a593Smuzhiyun  */
606*4882a593Smuzhiyun static struct gpiod_lookup_table crag_pmic_gpiod_table = {
607*4882a593Smuzhiyun 	.dev_id = "wm831x-buckv.11",
608*4882a593Smuzhiyun 	.table = {
609*4882a593Smuzhiyun 		GPIO_LOOKUP("GPIOK", 0, "dvs", GPIO_ACTIVE_HIGH),
610*4882a593Smuzhiyun 		{ },
611*4882a593Smuzhiyun 	},
612*4882a593Smuzhiyun };
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun static struct i2c_board_info i2c_devs0[] = {
615*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("24c08", 0x50), },
616*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("tca6408", 0x20),
617*4882a593Smuzhiyun 	  .platform_data = &crag6410_pca_data,
618*4882a593Smuzhiyun 	},
619*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("wm8312", 0x34),
620*4882a593Smuzhiyun 	  .platform_data = &crag_pmic_pdata,
621*4882a593Smuzhiyun 	  .irq = S3C_EINT(23),
622*4882a593Smuzhiyun 	},
623*4882a593Smuzhiyun };
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun static struct s3c2410_platform_i2c i2c0_pdata = {
626*4882a593Smuzhiyun 	.frequency = 400000,
627*4882a593Smuzhiyun };
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun static struct regulator_consumer_supply pvdd_1v2_consumers[] = {
630*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DCVDD", "spi0.0"),
631*4882a593Smuzhiyun 	REGULATOR_SUPPLY("AVDD", "spi0.0"),
632*4882a593Smuzhiyun 	REGULATOR_SUPPLY("AVDD", "spi0.1"),
633*4882a593Smuzhiyun };
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun static struct regulator_init_data pvdd_1v2 = {
636*4882a593Smuzhiyun 	.constraints = {
637*4882a593Smuzhiyun 		.name = "PVDD_1V2",
638*4882a593Smuzhiyun 		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
639*4882a593Smuzhiyun 	},
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	.consumer_supplies = pvdd_1v2_consumers,
642*4882a593Smuzhiyun 	.num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
643*4882a593Smuzhiyun };
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun static struct regulator_consumer_supply pvdd_1v8_consumers[] = {
646*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDOVDD", "1-001a"),
647*4882a593Smuzhiyun 	REGULATOR_SUPPLY("PLLVDD", "1-001a"),
648*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD", "1-001a"),
649*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD1", "1-001a"),
650*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD2", "1-001a"),
651*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD3", "1-001a"),
652*4882a593Smuzhiyun 	REGULATOR_SUPPLY("CPVDD", "1-001a"),
653*4882a593Smuzhiyun 	REGULATOR_SUPPLY("AVDD2", "1-001a"),
654*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DCVDD", "1-001a"),
655*4882a593Smuzhiyun 	REGULATOR_SUPPLY("AVDD", "1-001a"),
656*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD", "spi0.0"),
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD", "1-003a"),
659*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDOVDD", "1-003a"),
660*4882a593Smuzhiyun 	REGULATOR_SUPPLY("CPVDD", "1-003a"),
661*4882a593Smuzhiyun 	REGULATOR_SUPPLY("AVDD", "1-003a"),
662*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD1", "spi0.1"),
663*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD2", "spi0.1"),
664*4882a593Smuzhiyun 	REGULATOR_SUPPLY("DBVDD3", "spi0.1"),
665*4882a593Smuzhiyun 	REGULATOR_SUPPLY("LDOVDD", "spi0.1"),
666*4882a593Smuzhiyun 	REGULATOR_SUPPLY("CPVDD", "spi0.1"),
667*4882a593Smuzhiyun };
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun static struct regulator_init_data pvdd_1v8 = {
670*4882a593Smuzhiyun 	.constraints = {
671*4882a593Smuzhiyun 		.name = "PVDD_1V8",
672*4882a593Smuzhiyun 		.always_on = 1,
673*4882a593Smuzhiyun 	},
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	.consumer_supplies = pvdd_1v8_consumers,
676*4882a593Smuzhiyun 	.num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
677*4882a593Smuzhiyun };
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun static struct regulator_consumer_supply pvdd_3v3_consumers[] = {
680*4882a593Smuzhiyun 	REGULATOR_SUPPLY("MICVDD", "1-001a"),
681*4882a593Smuzhiyun 	REGULATOR_SUPPLY("AVDD1", "1-001a"),
682*4882a593Smuzhiyun };
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun static struct regulator_init_data pvdd_3v3 = {
685*4882a593Smuzhiyun 	.constraints = {
686*4882a593Smuzhiyun 		.name = "PVDD_3V3",
687*4882a593Smuzhiyun 		.always_on = 1,
688*4882a593Smuzhiyun 	},
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	.consumer_supplies = pvdd_3v3_consumers,
691*4882a593Smuzhiyun 	.num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
692*4882a593Smuzhiyun };
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun static struct wm831x_pdata glenfarclas_pmic_pdata = {
695*4882a593Smuzhiyun 	.wm831x_num = 2,
696*4882a593Smuzhiyun 	.irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
697*4882a593Smuzhiyun 	.gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
698*4882a593Smuzhiyun 	.soft_shutdown = true,
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	.gpio_defaults = {
701*4882a593Smuzhiyun 		/* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
702*4882a593Smuzhiyun 		[0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
703*4882a593Smuzhiyun 		[1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
704*4882a593Smuzhiyun 		[2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
705*4882a593Smuzhiyun 	},
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	.dcdc = {
708*4882a593Smuzhiyun 		&pvdd_1v2,  /* DCDC1 */
709*4882a593Smuzhiyun 		&pvdd_1v8,  /* DCDC2 */
710*4882a593Smuzhiyun 		&pvdd_3v3,  /* DCDC3 */
711*4882a593Smuzhiyun 	},
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 	.disable_touch = true,
714*4882a593Smuzhiyun };
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
717*4882a593Smuzhiyun 	.gpios = {
718*4882a593Smuzhiyun 		[WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
719*4882a593Smuzhiyun 		[WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
720*4882a593Smuzhiyun 		[WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
721*4882a593Smuzhiyun 		[WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
722*4882a593Smuzhiyun 		[WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
723*4882a593Smuzhiyun 	},
724*4882a593Smuzhiyun };
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun static struct i2c_board_info i2c_devs1[] = {
727*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("wm8311", 0x34),
728*4882a593Smuzhiyun 	  .irq = S3C_EINT(0),
729*4882a593Smuzhiyun 	  .platform_data = &glenfarclas_pmic_pdata },
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("wlf-gf-module", 0x20) },
732*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("wlf-gf-module", 0x22) },
733*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("wlf-gf-module", 0x24) },
734*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("wlf-gf-module", 0x25) },
735*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("wlf-gf-module", 0x26) },
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("wm1250-ev1", 0x27),
738*4882a593Smuzhiyun 	  .platform_data = &wm1250_ev1_pdata },
739*4882a593Smuzhiyun };
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun static struct s3c2410_platform_i2c i2c1_pdata = {
742*4882a593Smuzhiyun 	.frequency = 400000,
743*4882a593Smuzhiyun 	.bus_num = 1,
744*4882a593Smuzhiyun };
745*4882a593Smuzhiyun 
crag6410_map_io(void)746*4882a593Smuzhiyun static void __init crag6410_map_io(void)
747*4882a593Smuzhiyun {
748*4882a593Smuzhiyun 	s3c64xx_init_io(NULL, 0);
749*4882a593Smuzhiyun 	s3c64xx_set_xtal_freq(12000000);
750*4882a593Smuzhiyun 	s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
751*4882a593Smuzhiyun 	s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun 	/* LCD type and Bypass set by bootloader */
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
757*4882a593Smuzhiyun 	.max_width		= 4,
758*4882a593Smuzhiyun 	.cd_type		= S3C_SDHCI_CD_PERMANENT,
759*4882a593Smuzhiyun 	.host_caps		= MMC_CAP_POWER_OFF_CARD,
760*4882a593Smuzhiyun };
761*4882a593Smuzhiyun 
crag6410_cfg_sdhci0(struct platform_device * dev,int width)762*4882a593Smuzhiyun static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun 	/* Set all the necessary GPG pins to special-function 2 */
765*4882a593Smuzhiyun 	s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 	/* force card-detected for prototype 0 */
768*4882a593Smuzhiyun 	s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
772*4882a593Smuzhiyun 	.max_width		= 4,
773*4882a593Smuzhiyun 	.cd_type		= S3C_SDHCI_CD_INTERNAL,
774*4882a593Smuzhiyun 	.cfg_gpio		= crag6410_cfg_sdhci0,
775*4882a593Smuzhiyun 	.host_caps		= MMC_CAP_POWER_OFF_CARD,
776*4882a593Smuzhiyun };
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun static const struct gpio_led gpio_leds[] = {
779*4882a593Smuzhiyun 	{
780*4882a593Smuzhiyun 		.name = "d13:green:",
781*4882a593Smuzhiyun 		.gpio = MMGPIO_GPIO_BASE + 0,
782*4882a593Smuzhiyun 		.default_state = LEDS_GPIO_DEFSTATE_ON,
783*4882a593Smuzhiyun 	},
784*4882a593Smuzhiyun 	{
785*4882a593Smuzhiyun 		.name = "d14:green:",
786*4882a593Smuzhiyun 		.gpio = MMGPIO_GPIO_BASE + 1,
787*4882a593Smuzhiyun 		.default_state = LEDS_GPIO_DEFSTATE_ON,
788*4882a593Smuzhiyun 	},
789*4882a593Smuzhiyun 	{
790*4882a593Smuzhiyun 		.name = "d15:green:",
791*4882a593Smuzhiyun 		.gpio = MMGPIO_GPIO_BASE + 2,
792*4882a593Smuzhiyun 		.default_state = LEDS_GPIO_DEFSTATE_ON,
793*4882a593Smuzhiyun 	},
794*4882a593Smuzhiyun 	{
795*4882a593Smuzhiyun 		.name = "d16:green:",
796*4882a593Smuzhiyun 		.gpio = MMGPIO_GPIO_BASE + 3,
797*4882a593Smuzhiyun 		.default_state = LEDS_GPIO_DEFSTATE_ON,
798*4882a593Smuzhiyun 	},
799*4882a593Smuzhiyun 	{
800*4882a593Smuzhiyun 		.name = "d17:green:",
801*4882a593Smuzhiyun 		.gpio = MMGPIO_GPIO_BASE + 4,
802*4882a593Smuzhiyun 		.default_state = LEDS_GPIO_DEFSTATE_ON,
803*4882a593Smuzhiyun 	},
804*4882a593Smuzhiyun 	{
805*4882a593Smuzhiyun 		.name = "d18:green:",
806*4882a593Smuzhiyun 		.gpio = MMGPIO_GPIO_BASE + 5,
807*4882a593Smuzhiyun 		.default_state = LEDS_GPIO_DEFSTATE_ON,
808*4882a593Smuzhiyun 	},
809*4882a593Smuzhiyun 	{
810*4882a593Smuzhiyun 		.name = "d19:green:",
811*4882a593Smuzhiyun 		.gpio = MMGPIO_GPIO_BASE + 6,
812*4882a593Smuzhiyun 		.default_state = LEDS_GPIO_DEFSTATE_ON,
813*4882a593Smuzhiyun 	},
814*4882a593Smuzhiyun 	{
815*4882a593Smuzhiyun 		.name = "d20:green:",
816*4882a593Smuzhiyun 		.gpio = MMGPIO_GPIO_BASE + 7,
817*4882a593Smuzhiyun 		.default_state = LEDS_GPIO_DEFSTATE_ON,
818*4882a593Smuzhiyun 	},
819*4882a593Smuzhiyun };
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun static const struct gpio_led_platform_data gpio_leds_pdata = {
822*4882a593Smuzhiyun 	.leds = gpio_leds,
823*4882a593Smuzhiyun 	.num_leds = ARRAY_SIZE(gpio_leds),
824*4882a593Smuzhiyun };
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun static struct dwc2_hsotg_plat crag6410_hsotg_pdata;
827*4882a593Smuzhiyun 
crag6410_machine_init(void)828*4882a593Smuzhiyun static void __init crag6410_machine_init(void)
829*4882a593Smuzhiyun {
830*4882a593Smuzhiyun 	/* Open drain IRQs need pullups */
831*4882a593Smuzhiyun 	s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
832*4882a593Smuzhiyun 	s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun 	gpio_request(S3C64XX_GPB(0), "LCD power");
835*4882a593Smuzhiyun 	gpio_direction_output(S3C64XX_GPB(0), 0);
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 	gpio_request(S3C64XX_GPF(14), "LCD PWM");
838*4882a593Smuzhiyun 	gpio_direction_output(S3C64XX_GPF(14), 0);  /* turn off */
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 	gpio_request(S3C64XX_GPB(1), "SD power");
841*4882a593Smuzhiyun 	gpio_direction_output(S3C64XX_GPB(1), 0);
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 	gpio_request(S3C64XX_GPF(10), "nRESETSEL");
844*4882a593Smuzhiyun 	gpio_direction_output(S3C64XX_GPF(10), 1);
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun 	s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
847*4882a593Smuzhiyun 	s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	s3c_i2c0_set_platdata(&i2c0_pdata);
850*4882a593Smuzhiyun 	s3c_i2c1_set_platdata(&i2c1_pdata);
851*4882a593Smuzhiyun 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
852*4882a593Smuzhiyun 	dwc2_hsotg_set_platdata(&crag6410_hsotg_pdata);
853*4882a593Smuzhiyun 
854*4882a593Smuzhiyun 	gpiod_add_lookup_table(&crag_pmic_gpiod_table);
855*4882a593Smuzhiyun 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
856*4882a593Smuzhiyun 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun 	samsung_keypad_set_platdata(&crag6410_keypad_data);
859*4882a593Smuzhiyun 	s3c64xx_spi0_set_platdata(NULL, 0, 2);
860*4882a593Smuzhiyun 
861*4882a593Smuzhiyun 	pwm_add_table(crag6410_pwm_lookup, ARRAY_SIZE(crag6410_pwm_lookup));
862*4882a593Smuzhiyun 	platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 	gpio_led_register_device(-1, &gpio_leds_pdata);
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 	regulator_has_full_constraints();
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun 	s3c64xx_pm_init();
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
872*4882a593Smuzhiyun 	/* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
873*4882a593Smuzhiyun 	.atag_offset	= 0x100,
874*4882a593Smuzhiyun 	.nr_irqs	= S3C64XX_NR_IRQS,
875*4882a593Smuzhiyun 	.init_irq	= s3c6410_init_irq,
876*4882a593Smuzhiyun 	.map_io		= crag6410_map_io,
877*4882a593Smuzhiyun 	.init_machine	= crag6410_machine_init,
878*4882a593Smuzhiyun 	.init_time	= s3c64xx_timer_init,
879*4882a593Smuzhiyun MACHINE_END
880