1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2003-2004 Simtec Electronics
4*4882a593Smuzhiyun // Ben Dooks <ben@simtec.co.uk>
5*4882a593Smuzhiyun // http://armlinux.simtec.co.uk/
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // S3C24XX - IRQ PM code
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/syscore_ops.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "cpu.h"
17*4882a593Smuzhiyun #include "pm.h"
18*4882a593Smuzhiyun #include <mach/map-base.h>
19*4882a593Smuzhiyun #include "map-s3c.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "regs-irq.h"
22*4882a593Smuzhiyun #include "regs-gpio.h"
23*4882a593Smuzhiyun #include "pm-core.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <asm/irq.h>
26*4882a593Smuzhiyun
s3c_irq_wake(struct irq_data * data,unsigned int state)27*4882a593Smuzhiyun int s3c_irq_wake(struct irq_data *data, unsigned int state)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun unsigned long irqbit = 1 << data->hwirq;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (!(s3c_irqwake_intallow & irqbit))
32*4882a593Smuzhiyun return -ENOENT;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun pr_info("wake %s for hwirq %lu\n",
35*4882a593Smuzhiyun state ? "enabled" : "disabled", data->hwirq);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun if (!state)
38*4882a593Smuzhiyun s3c_irqwake_intmask |= irqbit;
39*4882a593Smuzhiyun else
40*4882a593Smuzhiyun s3c_irqwake_intmask &= ~irqbit;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return 0;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static struct sleep_save irq_save[] = {
46*4882a593Smuzhiyun SAVE_ITEM(S3C2410_INTMSK),
47*4882a593Smuzhiyun SAVE_ITEM(S3C2410_INTSUBMSK),
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* the extint values move between the s3c2410/s3c2440 and the s3c2412
51*4882a593Smuzhiyun * so we use an array to hold them, and to calculate the address of
52*4882a593Smuzhiyun * the register at run-time
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static unsigned long save_extint[3];
56*4882a593Smuzhiyun static unsigned long save_eintflt[4];
57*4882a593Smuzhiyun static unsigned long save_eintmask;
58*4882a593Smuzhiyun
s3c24xx_irq_suspend(void)59*4882a593Smuzhiyun static int s3c24xx_irq_suspend(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun unsigned int i;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(save_extint); i++)
64*4882a593Smuzhiyun save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
67*4882a593Smuzhiyun save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
70*4882a593Smuzhiyun save_eintmask = __raw_readl(S3C24XX_EINTMASK);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
s3c24xx_irq_resume(void)75*4882a593Smuzhiyun static void s3c24xx_irq_resume(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun unsigned int i;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(save_extint); i++)
80*4882a593Smuzhiyun __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
83*4882a593Smuzhiyun __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
86*4882a593Smuzhiyun __raw_writel(save_eintmask, S3C24XX_EINTMASK);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun struct syscore_ops s3c24xx_irq_syscore_ops = {
90*4882a593Smuzhiyun .suspend = s3c24xx_irq_suspend,
91*4882a593Smuzhiyun .resume = s3c24xx_irq_resume,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #ifdef CONFIG_CPU_S3C2416
95*4882a593Smuzhiyun static struct sleep_save s3c2416_irq_save[] = {
96*4882a593Smuzhiyun SAVE_ITEM(S3C2416_INTMSK2),
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
s3c2416_irq_suspend(void)99*4882a593Smuzhiyun static int s3c2416_irq_suspend(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
s3c2416_irq_resume(void)106*4882a593Smuzhiyun static void s3c2416_irq_resume(void)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun struct syscore_ops s3c2416_irq_syscore_ops = {
112*4882a593Smuzhiyun .suspend = s3c2416_irq_suspend,
113*4882a593Smuzhiyun .resume = s3c2416_irq_resume,
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun #endif
116