1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2008 Simtec Electronics
4*4882a593Smuzhiyun // Ben Dooks <ben@simtec.co.uk>
5*4882a593Smuzhiyun // http://armlinux.simtec.co.uk/
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // S3C series CPU initialisation
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun * NOTE: Code in this file is not used on S3C64xx when booting with
11*4882a593Smuzhiyun * Device Tree support.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/ioport.h>
18*4882a593Smuzhiyun #include <linux/serial_core.h>
19*4882a593Smuzhiyun #include <linux/serial_s3c.h>
20*4882a593Smuzhiyun #include <linux/platform_device.h>
21*4882a593Smuzhiyun #include <linux/of.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <asm/mach/arch.h>
24*4882a593Smuzhiyun #include <asm/mach/map.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "cpu.h"
27*4882a593Smuzhiyun #include "devs.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static struct cpu_table *cpu;
30*4882a593Smuzhiyun
s3c_lookup_cpu(unsigned long idcode,struct cpu_table * tab,unsigned int count)31*4882a593Smuzhiyun static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
32*4882a593Smuzhiyun struct cpu_table *tab,
33*4882a593Smuzhiyun unsigned int count)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun for (; count != 0; count--, tab++) {
36*4882a593Smuzhiyun if ((idcode & tab->idmask) == (tab->idcode & tab->idmask))
37*4882a593Smuzhiyun return tab;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return NULL;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
s3c_init_cpu(unsigned long idcode,struct cpu_table * cputab,unsigned int cputab_size)43*4882a593Smuzhiyun void __init s3c_init_cpu(unsigned long idcode,
44*4882a593Smuzhiyun struct cpu_table *cputab, unsigned int cputab_size)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun cpu = s3c_lookup_cpu(idcode, cputab, cputab_size);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (cpu == NULL) {
49*4882a593Smuzhiyun printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
50*4882a593Smuzhiyun panic("Unknown S3C24XX CPU");
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (cpu->init == NULL) {
56*4882a593Smuzhiyun printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
57*4882a593Smuzhiyun panic("Unsupported Samsung CPU");
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (cpu->map_io)
61*4882a593Smuzhiyun cpu->map_io();
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* s3c24xx_init_clocks
65*4882a593Smuzhiyun *
66*4882a593Smuzhiyun * Initialise the clock subsystem and associated information from the
67*4882a593Smuzhiyun * given master crystal value.
68*4882a593Smuzhiyun *
69*4882a593Smuzhiyun * xtal = 0 -> use default PLL crystal value (normally 12MHz)
70*4882a593Smuzhiyun * != 0 -> PLL crystal value in Hz
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun
s3c24xx_init_clocks(int xtal)73*4882a593Smuzhiyun void __init s3c24xx_init_clocks(int xtal)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun if (xtal == 0)
76*4882a593Smuzhiyun xtal = 12*1000*1000;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (cpu == NULL)
79*4882a593Smuzhiyun panic("s3c24xx_init_clocks: no cpu setup?\n");
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (cpu->init_clocks == NULL)
82*4882a593Smuzhiyun panic("s3c24xx_init_clocks: cpu has no clock init\n");
83*4882a593Smuzhiyun else
84*4882a593Smuzhiyun (cpu->init_clocks)(xtal);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* uart management */
88*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
89*4882a593Smuzhiyun static int nr_uarts __initdata = 0;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_SAMSUNG_UARTS
92*4882a593Smuzhiyun static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
93*4882a593Smuzhiyun #endif
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* s3c24xx_init_uartdevs
96*4882a593Smuzhiyun *
97*4882a593Smuzhiyun * copy the specified platform data and configuration into our central
98*4882a593Smuzhiyun * set of devices, before the data is thrown away after the init process.
99*4882a593Smuzhiyun *
100*4882a593Smuzhiyun * This also fills in the array passed to the serial driver for the
101*4882a593Smuzhiyun * early initialisation of the console.
102*4882a593Smuzhiyun */
103*4882a593Smuzhiyun
s3c24xx_init_uartdevs(char * name,struct s3c24xx_uart_resources * res,struct s3c2410_uartcfg * cfg,int no)104*4882a593Smuzhiyun void __init s3c24xx_init_uartdevs(char *name,
105*4882a593Smuzhiyun struct s3c24xx_uart_resources *res,
106*4882a593Smuzhiyun struct s3c2410_uartcfg *cfg, int no)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_SAMSUNG_UARTS
109*4882a593Smuzhiyun struct platform_device *platdev;
110*4882a593Smuzhiyun struct s3c2410_uartcfg *cfgptr = uart_cfgs;
111*4882a593Smuzhiyun struct s3c24xx_uart_resources *resp;
112*4882a593Smuzhiyun int uart;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
117*4882a593Smuzhiyun platdev = s3c24xx_uart_src[cfgptr->hwport];
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun resp = res + cfgptr->hwport;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun s3c24xx_uart_devs[uart] = platdev;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun platdev->name = name;
124*4882a593Smuzhiyun platdev->resource = resp->resources;
125*4882a593Smuzhiyun platdev->num_resources = resp->nr_resources;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun platdev->dev.platform_data = cfgptr;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun nr_uarts = no;
131*4882a593Smuzhiyun #endif
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
s3c24xx_init_uarts(struct s3c2410_uartcfg * cfg,int no)134*4882a593Smuzhiyun void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun if (cpu == NULL)
137*4882a593Smuzhiyun return;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) {
140*4882a593Smuzhiyun printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
141*4882a593Smuzhiyun } else
142*4882a593Smuzhiyun (cpu->init_uarts)(cfg, no);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun #endif
145*4882a593Smuzhiyun
s3c_arch_init(void)146*4882a593Smuzhiyun static int __init s3c_arch_init(void)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun int ret;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* init is only needed for ATAGS based platforms */
151*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_ATAGS) ||
152*4882a593Smuzhiyun (!soc_is_s3c24xx() && !soc_is_s3c64xx()))
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun // do the correct init for cpu
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun if (cpu == NULL) {
158*4882a593Smuzhiyun /* Not needed when booting with device tree. */
159*4882a593Smuzhiyun if (of_have_populated_dt())
160*4882a593Smuzhiyun return 0;
161*4882a593Smuzhiyun panic("s3c_arch_init: NULL cpu\n");
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun ret = (cpu->init)();
165*4882a593Smuzhiyun if (ret != 0)
166*4882a593Smuzhiyun return ret;
167*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
168*4882a593Smuzhiyun ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
169*4882a593Smuzhiyun #endif
170*4882a593Smuzhiyun return ret;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun arch_initcall(s3c_arch_init);
174