1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2003, 2007 Simtec Electronics 4*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 5*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * S3C - Memory map definitions (virtual addresses) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_PLAT_MAP_H 11*4882a593Smuzhiyun #define __ASM_PLAT_MAP_H __FILE__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Fit all our registers in at 0xF6000000 upwards, trying to use as 14*4882a593Smuzhiyun * little of the VA space as possible so vmalloc and friends have a 15*4882a593Smuzhiyun * better chance of getting memory. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * we try to ensure stuff like the IRQ registers are available for 18*4882a593Smuzhiyun * an single MOVS instruction (ie, only 8 bits of set data) 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define S3C_ADDR_BASE 0xF6000000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 24*4882a593Smuzhiyun #define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) 25*4882a593Smuzhiyun #else 26*4882a593Smuzhiyun #define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ 30*4882a593Smuzhiyun #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ 31*4882a593Smuzhiyun #define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ 32*4882a593Smuzhiyun #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ 33*4882a593Smuzhiyun #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ 34*4882a593Smuzhiyun #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* This is used for the CPU specific mappings that may be needed, so that 37*4882a593Smuzhiyun * they do not need to directly used S3C_ADDR() and thus make it easier to 38*4882a593Smuzhiyun * modify the space for mapping. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif /* __ASM_PLAT_MAP_H */ 43