1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2003-2005 Simtec Electronics 4*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_ARCH_IRQS_H 9*4882a593Smuzhiyun #define __ASM_ARCH_IRQS_H __FILE__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* we keep the first set of CPU IRQs out of the range of 12*4882a593Smuzhiyun * the ISA space, so that the PC104 has them to itself 13*4882a593Smuzhiyun * and we don't end up having to do horrible things to the 14*4882a593Smuzhiyun * standard ISA drivers.... 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define S3C2410_CPUIRQ_OFFSET (16) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* main cpu interrupts */ 22*4882a593Smuzhiyun #define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ 23*4882a593Smuzhiyun #define IRQ_EINT1 S3C2410_IRQ(1) 24*4882a593Smuzhiyun #define IRQ_EINT2 S3C2410_IRQ(2) 25*4882a593Smuzhiyun #define IRQ_EINT3 S3C2410_IRQ(3) 26*4882a593Smuzhiyun #define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ 27*4882a593Smuzhiyun #define IRQ_EINT8t23 S3C2410_IRQ(5) 28*4882a593Smuzhiyun #define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ 29*4882a593Smuzhiyun #define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ 30*4882a593Smuzhiyun #define IRQ_BATT_FLT S3C2410_IRQ(7) 31*4882a593Smuzhiyun #define IRQ_TICK S3C2410_IRQ(8) /* 24 */ 32*4882a593Smuzhiyun #define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ 33*4882a593Smuzhiyun #define IRQ_TIMER0 S3C2410_IRQ(10) 34*4882a593Smuzhiyun #define IRQ_TIMER1 S3C2410_IRQ(11) 35*4882a593Smuzhiyun #define IRQ_TIMER2 S3C2410_IRQ(12) 36*4882a593Smuzhiyun #define IRQ_TIMER3 S3C2410_IRQ(13) 37*4882a593Smuzhiyun #define IRQ_TIMER4 S3C2410_IRQ(14) 38*4882a593Smuzhiyun #define IRQ_UART2 S3C2410_IRQ(15) 39*4882a593Smuzhiyun #define IRQ_LCD S3C2410_IRQ(16) /* 32 */ 40*4882a593Smuzhiyun #define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ 41*4882a593Smuzhiyun #define IRQ_DMA1 S3C2410_IRQ(18) 42*4882a593Smuzhiyun #define IRQ_DMA2 S3C2410_IRQ(19) 43*4882a593Smuzhiyun #define IRQ_DMA3 S3C2410_IRQ(20) 44*4882a593Smuzhiyun #define IRQ_SDI S3C2410_IRQ(21) 45*4882a593Smuzhiyun #define IRQ_SPI0 S3C2410_IRQ(22) 46*4882a593Smuzhiyun #define IRQ_UART1 S3C2410_IRQ(23) 47*4882a593Smuzhiyun #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ 48*4882a593Smuzhiyun #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ 49*4882a593Smuzhiyun #define IRQ_USBD S3C2410_IRQ(25) 50*4882a593Smuzhiyun #define IRQ_USBH S3C2410_IRQ(26) 51*4882a593Smuzhiyun #define IRQ_IIC S3C2410_IRQ(27) 52*4882a593Smuzhiyun #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ 53*4882a593Smuzhiyun #define IRQ_SPI1 S3C2410_IRQ(29) 54*4882a593Smuzhiyun #define IRQ_RTC S3C2410_IRQ(30) 55*4882a593Smuzhiyun #define IRQ_ADCPARENT S3C2410_IRQ(31) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* interrupts generated from the external interrupts sources */ 58*4882a593Smuzhiyun #define IRQ_EINT0_2412 S3C2410_IRQ(32) 59*4882a593Smuzhiyun #define IRQ_EINT1_2412 S3C2410_IRQ(33) 60*4882a593Smuzhiyun #define IRQ_EINT2_2412 S3C2410_IRQ(34) 61*4882a593Smuzhiyun #define IRQ_EINT3_2412 S3C2410_IRQ(35) 62*4882a593Smuzhiyun #define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ 63*4882a593Smuzhiyun #define IRQ_EINT5 S3C2410_IRQ(37) 64*4882a593Smuzhiyun #define IRQ_EINT6 S3C2410_IRQ(38) 65*4882a593Smuzhiyun #define IRQ_EINT7 S3C2410_IRQ(39) 66*4882a593Smuzhiyun #define IRQ_EINT8 S3C2410_IRQ(40) 67*4882a593Smuzhiyun #define IRQ_EINT9 S3C2410_IRQ(41) 68*4882a593Smuzhiyun #define IRQ_EINT10 S3C2410_IRQ(42) 69*4882a593Smuzhiyun #define IRQ_EINT11 S3C2410_IRQ(43) 70*4882a593Smuzhiyun #define IRQ_EINT12 S3C2410_IRQ(44) 71*4882a593Smuzhiyun #define IRQ_EINT13 S3C2410_IRQ(45) 72*4882a593Smuzhiyun #define IRQ_EINT14 S3C2410_IRQ(46) 73*4882a593Smuzhiyun #define IRQ_EINT15 S3C2410_IRQ(47) 74*4882a593Smuzhiyun #define IRQ_EINT16 S3C2410_IRQ(48) 75*4882a593Smuzhiyun #define IRQ_EINT17 S3C2410_IRQ(49) 76*4882a593Smuzhiyun #define IRQ_EINT18 S3C2410_IRQ(50) 77*4882a593Smuzhiyun #define IRQ_EINT19 S3C2410_IRQ(51) 78*4882a593Smuzhiyun #define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */ 79*4882a593Smuzhiyun #define IRQ_EINT21 S3C2410_IRQ(53) 80*4882a593Smuzhiyun #define IRQ_EINT22 S3C2410_IRQ(54) 81*4882a593Smuzhiyun #define IRQ_EINT23 S3C2410_IRQ(55) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) 84*4882a593Smuzhiyun #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define IRQ_LCD_FIFO S3C2410_IRQ(56) 87*4882a593Smuzhiyun #define IRQ_LCD_FRAME S3C2410_IRQ(57) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* IRQs for the interal UARTs, and ADC 90*4882a593Smuzhiyun * these need to be ordered in number of appearance in the 91*4882a593Smuzhiyun * SUBSRC mask register 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */ 97*4882a593Smuzhiyun #define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) 98*4882a593Smuzhiyun #define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */ 101*4882a593Smuzhiyun #define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) 102*4882a593Smuzhiyun #define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */ 105*4882a593Smuzhiyun #define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) 106*4882a593Smuzhiyun #define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define IRQ_TC S3C2410_IRQSUB(9) 109*4882a593Smuzhiyun #define IRQ_ADC S3C2410_IRQSUB(10) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* extra irqs for s3c2412 */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) 116*4882a593Smuzhiyun #define IRQ_S3C2412_CF S3C2410_IRQSUB(14) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) 120*4882a593Smuzhiyun #define IRQ_S3C2416_DMA S3C2410_IRQ(17) 121*4882a593Smuzhiyun #define IRQ_S3C2416_UART3 S3C2410_IRQ(18) 122*4882a593Smuzhiyun #define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) 123*4882a593Smuzhiyun #define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) 126*4882a593Smuzhiyun #define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) 127*4882a593Smuzhiyun #define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) 128*4882a593Smuzhiyun #define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) 129*4882a593Smuzhiyun #define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) 130*4882a593Smuzhiyun #define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) 131*4882a593Smuzhiyun #define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) 132*4882a593Smuzhiyun #define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) 133*4882a593Smuzhiyun #define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) 134*4882a593Smuzhiyun #define IRQ_S32416_WDT S3C2410_IRQSUB(27) 135*4882a593Smuzhiyun #define IRQ_S32416_AC97 S3C2410_IRQSUB(28) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* second interrupt-register of s3c2416/s3c2450 */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29) 140*4882a593Smuzhiyun #define IRQ_S3C2416_2D S3C2416_IRQ(0) 141*4882a593Smuzhiyun #define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) 142*4882a593Smuzhiyun #define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) 143*4882a593Smuzhiyun #define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3) 144*4882a593Smuzhiyun #define IRQ_S3C2416_PCM0 S3C2416_IRQ(4) 145*4882a593Smuzhiyun #define IRQ_S3C2416_PCM1 S3C2416_IRQ(5) 146*4882a593Smuzhiyun #define IRQ_S3C2416_I2S0 S3C2416_IRQ(6) 147*4882a593Smuzhiyun #define IRQ_S3C2416_I2S1 S3C2416_IRQ(7) 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* extra irqs for s3c2440 */ 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ 152*4882a593Smuzhiyun #define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ 153*4882a593Smuzhiyun #define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) 154*4882a593Smuzhiyun #define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* irqs for s3c2443 */ 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ 159*4882a593Smuzhiyun #define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ 160*4882a593Smuzhiyun #define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ 161*4882a593Smuzhiyun #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ 162*4882a593Smuzhiyun #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 167*4882a593Smuzhiyun #define IRQ_HSMMC1 IRQ_S3C2443_HSMMC 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) 170*4882a593Smuzhiyun #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) 171*4882a593Smuzhiyun #define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) 172*4882a593Smuzhiyun #define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) 175*4882a593Smuzhiyun #define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) 176*4882a593Smuzhiyun #define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) 177*4882a593Smuzhiyun #define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) 178*4882a593Smuzhiyun #define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) 179*4882a593Smuzhiyun #define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* UART3 */ 182*4882a593Smuzhiyun #define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) 183*4882a593Smuzhiyun #define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) 184*4882a593Smuzhiyun #define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) 187*4882a593Smuzhiyun #define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #if defined(CONFIG_CPU_S3C2416) 190*4882a593Smuzhiyun #define NR_IRQS (IRQ_S3C2416_I2S1 + 1) 191*4882a593Smuzhiyun #else 192*4882a593Smuzhiyun #define NR_IRQS (IRQ_S3C2443_AC97 + 1) 193*4882a593Smuzhiyun #endif 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* compatibility define. */ 196*4882a593Smuzhiyun #define IRQ_UART3 IRQ_S3C2443_UART3 197*4882a593Smuzhiyun #define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 198*4882a593Smuzhiyun #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 199*4882a593Smuzhiyun #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 202*4882a593Smuzhiyun #define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #ifdef CONFIG_CPU_S3C2440 205*4882a593Smuzhiyun #define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 206*4882a593Smuzhiyun #else 207*4882a593Smuzhiyun #define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 208*4882a593Smuzhiyun #endif 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ 211*4882a593Smuzhiyun #define FIQ_START IRQ_EINT0 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #endif /* __ASM_ARCH_IRQ_H */ 214