1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-s3c2410/include/mach/io.h 4*4882a593Smuzhiyun * from arch/arm/mach-rpc/include/mach/io.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1997 Russell King 7*4882a593Smuzhiyun * (C) 2003 Simtec Electronics 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARM_ARCH_IO_S3C24XX_H 11*4882a593Smuzhiyun #define __ASM_ARM_ARCH_IO_S3C24XX_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <mach/map-base.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * ISA style IO, for each machine to sort out mappings for, 17*4882a593Smuzhiyun * if it implements it. We reserve two 16M regions for ISA, 18*4882a593Smuzhiyun * so the PC/104 can use separate addresses for 8-bit and 19*4882a593Smuzhiyun * 16-bit port I/O. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define PCIO_BASE S3C_ADDR(0x02000000) 22*4882a593Smuzhiyun #define IO_SPACE_LIMIT 0x00ffffff 23*4882a593Smuzhiyun #define S3C24XX_VA_ISA_WORD (PCIO_BASE) 24*4882a593Smuzhiyun #define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifdef CONFIG_ISA 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p)) 29*4882a593Smuzhiyun #define inw(p) readw(S3C24XX_VA_ISA_WORD + (p)) 30*4882a593Smuzhiyun #define inl(p) readl(S3C24XX_VA_ISA_WORD + (p)) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p)) 33*4882a593Smuzhiyun #define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p)) 34*4882a593Smuzhiyun #define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p)) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l) 37*4882a593Smuzhiyun #define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l) 38*4882a593Smuzhiyun #define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l) 41*4882a593Smuzhiyun #define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l) 42*4882a593Smuzhiyun #define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #else 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define __io(x) (PCIO_BASE + (x)) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51