1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2008 Openmoko, Inc. 4*4882a593Smuzhiyun * Copyright 2008 Simtec Electronics 5*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 6*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * S3C6400 - GPIO lib support 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef GPIO_SAMSUNG_S3C64XX_H 12*4882a593Smuzhiyun #define GPIO_SAMSUNG_S3C64XX_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifdef CONFIG_GPIO_SAMSUNG 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* GPIO bank sizes */ 17*4882a593Smuzhiyun #define S3C64XX_GPIO_A_NR (8) 18*4882a593Smuzhiyun #define S3C64XX_GPIO_B_NR (7) 19*4882a593Smuzhiyun #define S3C64XX_GPIO_C_NR (8) 20*4882a593Smuzhiyun #define S3C64XX_GPIO_D_NR (5) 21*4882a593Smuzhiyun #define S3C64XX_GPIO_E_NR (5) 22*4882a593Smuzhiyun #define S3C64XX_GPIO_F_NR (16) 23*4882a593Smuzhiyun #define S3C64XX_GPIO_G_NR (7) 24*4882a593Smuzhiyun #define S3C64XX_GPIO_H_NR (10) 25*4882a593Smuzhiyun #define S3C64XX_GPIO_I_NR (16) 26*4882a593Smuzhiyun #define S3C64XX_GPIO_J_NR (12) 27*4882a593Smuzhiyun #define S3C64XX_GPIO_K_NR (16) 28*4882a593Smuzhiyun #define S3C64XX_GPIO_L_NR (15) 29*4882a593Smuzhiyun #define S3C64XX_GPIO_M_NR (6) 30*4882a593Smuzhiyun #define S3C64XX_GPIO_N_NR (16) 31*4882a593Smuzhiyun #define S3C64XX_GPIO_O_NR (16) 32*4882a593Smuzhiyun #define S3C64XX_GPIO_P_NR (15) 33*4882a593Smuzhiyun #define S3C64XX_GPIO_Q_NR (9) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* GPIO bank numbes */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* CONFIG_S3C_GPIO_SPACE allows the user to select extra 38*4882a593Smuzhiyun * space for debugging purposes so that any accidental 39*4882a593Smuzhiyun * change from one gpio bank to another can be caught. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define S3C64XX_GPIO_NEXT(__gpio) \ 43*4882a593Smuzhiyun ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum s3c_gpio_number { 46*4882a593Smuzhiyun S3C64XX_GPIO_A_START = 0, 47*4882a593Smuzhiyun S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A), 48*4882a593Smuzhiyun S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B), 49*4882a593Smuzhiyun S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C), 50*4882a593Smuzhiyun S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D), 51*4882a593Smuzhiyun S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E), 52*4882a593Smuzhiyun S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F), 53*4882a593Smuzhiyun S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G), 54*4882a593Smuzhiyun S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H), 55*4882a593Smuzhiyun S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I), 56*4882a593Smuzhiyun S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J), 57*4882a593Smuzhiyun S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K), 58*4882a593Smuzhiyun S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L), 59*4882a593Smuzhiyun S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M), 60*4882a593Smuzhiyun S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N), 61*4882a593Smuzhiyun S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O), 62*4882a593Smuzhiyun S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P), 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* S3C64XX GPIO number definitions. */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr)) 68*4882a593Smuzhiyun #define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr)) 69*4882a593Smuzhiyun #define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr)) 70*4882a593Smuzhiyun #define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr)) 71*4882a593Smuzhiyun #define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr)) 72*4882a593Smuzhiyun #define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr)) 73*4882a593Smuzhiyun #define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr)) 74*4882a593Smuzhiyun #define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr)) 75*4882a593Smuzhiyun #define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr)) 76*4882a593Smuzhiyun #define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr)) 77*4882a593Smuzhiyun #define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr)) 78*4882a593Smuzhiyun #define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr)) 79*4882a593Smuzhiyun #define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr)) 80*4882a593Smuzhiyun #define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr)) 81*4882a593Smuzhiyun #define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr)) 82*4882a593Smuzhiyun #define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr)) 83*4882a593Smuzhiyun #define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr)) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* the end of the S3C64XX specific gpios */ 86*4882a593Smuzhiyun #define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) 87*4882a593Smuzhiyun #define S3C_GPIO_END S3C64XX_GPIO_END 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* define the number of gpios we need to the one after the GPQ() range */ 90*4882a593Smuzhiyun #define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* GPIO_SAMSUNG */ 93*4882a593Smuzhiyun #endif /* GPIO_SAMSUNG_S3C64XX_H */ 94*4882a593Smuzhiyun 95