1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2003-2006 Simtec Electronics 4*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Samsung S3C24XX DMA support 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_DMA_H 10*4882a593Smuzhiyun #define __ASM_ARCH_DMA_H __FILE__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/device.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* We use `virtual` dma channels to hide the fact we have only a limited 15*4882a593Smuzhiyun * number of DMA channels, and not of all of them (dependent on the device) 16*4882a593Smuzhiyun * can be attached to any DMA source. We therefore let the DMA core handle 17*4882a593Smuzhiyun * the allocation of hardware channels to clients. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum dma_ch { 21*4882a593Smuzhiyun DMACH_XD0 = 0, 22*4882a593Smuzhiyun DMACH_XD1, 23*4882a593Smuzhiyun DMACH_SDI, 24*4882a593Smuzhiyun DMACH_SPI0, 25*4882a593Smuzhiyun DMACH_SPI1, 26*4882a593Smuzhiyun DMACH_UART0, 27*4882a593Smuzhiyun DMACH_UART1, 28*4882a593Smuzhiyun DMACH_UART2, 29*4882a593Smuzhiyun DMACH_TIMER, 30*4882a593Smuzhiyun DMACH_I2S_IN, 31*4882a593Smuzhiyun DMACH_I2S_OUT, 32*4882a593Smuzhiyun DMACH_PCM_IN, 33*4882a593Smuzhiyun DMACH_PCM_OUT, 34*4882a593Smuzhiyun DMACH_MIC_IN, 35*4882a593Smuzhiyun DMACH_USB_EP1, 36*4882a593Smuzhiyun DMACH_USB_EP2, 37*4882a593Smuzhiyun DMACH_USB_EP3, 38*4882a593Smuzhiyun DMACH_USB_EP4, 39*4882a593Smuzhiyun DMACH_UART0_SRC2, /* s3c2412 second uart sources */ 40*4882a593Smuzhiyun DMACH_UART1_SRC2, 41*4882a593Smuzhiyun DMACH_UART2_SRC2, 42*4882a593Smuzhiyun DMACH_UART3, /* s3c2443 has extra uart */ 43*4882a593Smuzhiyun DMACH_UART3_SRC2, 44*4882a593Smuzhiyun DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */ 45*4882a593Smuzhiyun DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */ 46*4882a593Smuzhiyun DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */ 47*4882a593Smuzhiyun DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */ 48*4882a593Smuzhiyun DMACH_MAX, /* the end entry */ 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* __ASM_ARCH_DMA_H */ 52