1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright 2003-2005 Simtec Electronics
4*4882a593Smuzhiyun // Ben Dooks <ben@simtec.co.uk>
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // http://www.simtec.co.uk/products/EB2410ITX/
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/ioport.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/irq.h>
15*4882a593Smuzhiyun #include <asm/mach-types.h>
16*4882a593Smuzhiyun #include <asm/mach/irq.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "regs-irq.h"
19*4882a593Smuzhiyun #include <mach/irqs.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "bast.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define irqdbf(x...)
24*4882a593Smuzhiyun #define irqdbf2(x...)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* handle PC104 ISA interrupts from the system CPLD */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* table of ISA irq nos to the relevant mask... zero means
29*4882a593Smuzhiyun * the irq is not implemented
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun static const unsigned char bast_pc104_irqmasks[] = {
32*4882a593Smuzhiyun 0, /* 0 */
33*4882a593Smuzhiyun 0, /* 1 */
34*4882a593Smuzhiyun 0, /* 2 */
35*4882a593Smuzhiyun 1, /* 3 */
36*4882a593Smuzhiyun 0, /* 4 */
37*4882a593Smuzhiyun 2, /* 5 */
38*4882a593Smuzhiyun 0, /* 6 */
39*4882a593Smuzhiyun 4, /* 7 */
40*4882a593Smuzhiyun 0, /* 8 */
41*4882a593Smuzhiyun 0, /* 9 */
42*4882a593Smuzhiyun 8, /* 10 */
43*4882a593Smuzhiyun 0, /* 11 */
44*4882a593Smuzhiyun 0, /* 12 */
45*4882a593Smuzhiyun 0, /* 13 */
46*4882a593Smuzhiyun 0, /* 14 */
47*4882a593Smuzhiyun 0, /* 15 */
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static void
bast_pc104_mask(struct irq_data * data)53*4882a593Smuzhiyun bast_pc104_mask(struct irq_data *data)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun unsigned long temp;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun temp = __raw_readb(BAST_VA_PC104_IRQMASK);
58*4882a593Smuzhiyun temp &= ~bast_pc104_irqmasks[data->irq];
59*4882a593Smuzhiyun __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static void
bast_pc104_maskack(struct irq_data * data)63*4882a593Smuzhiyun bast_pc104_maskack(struct irq_data *data)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct irq_desc *desc = irq_to_desc(BAST_IRQ_ISA);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun bast_pc104_mask(data);
68*4882a593Smuzhiyun desc->irq_data.chip->irq_ack(&desc->irq_data);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static void
bast_pc104_unmask(struct irq_data * data)72*4882a593Smuzhiyun bast_pc104_unmask(struct irq_data *data)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun unsigned long temp;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun temp = __raw_readb(BAST_VA_PC104_IRQMASK);
77*4882a593Smuzhiyun temp |= bast_pc104_irqmasks[data->irq];
78*4882a593Smuzhiyun __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static struct irq_chip bast_pc104_chip = {
82*4882a593Smuzhiyun .irq_mask = bast_pc104_mask,
83*4882a593Smuzhiyun .irq_unmask = bast_pc104_unmask,
84*4882a593Smuzhiyun .irq_ack = bast_pc104_maskack
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
bast_irq_pc104_demux(struct irq_desc * desc)87*4882a593Smuzhiyun static void bast_irq_pc104_demux(struct irq_desc *desc)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun unsigned int stat;
90*4882a593Smuzhiyun unsigned int irqno;
91*4882a593Smuzhiyun int i;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun if (unlikely(stat == 0)) {
96*4882a593Smuzhiyun /* ack if we get an irq with nothing (ie, startup) */
97*4882a593Smuzhiyun desc->irq_data.chip->irq_ack(&desc->irq_data);
98*4882a593Smuzhiyun } else {
99*4882a593Smuzhiyun /* handle the IRQ */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun for (i = 0; stat != 0; i++, stat >>= 1) {
102*4882a593Smuzhiyun if (stat & 1) {
103*4882a593Smuzhiyun irqno = bast_pc104_irqs[i];
104*4882a593Smuzhiyun generic_handle_irq(irqno);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
bast_irq_init(void)110*4882a593Smuzhiyun static __init int bast_irq_init(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun unsigned int i;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (machine_is_bast()) {
115*4882a593Smuzhiyun printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* zap all the IRQs */
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* register our IRQs */
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
126*4882a593Smuzhiyun unsigned int irqno = bast_pc104_irqs[i];
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun irq_set_chip_and_handler(irqno, &bast_pc104_chip,
129*4882a593Smuzhiyun handle_level_irq);
130*4882a593Smuzhiyun irq_clear_status_flags(irqno, IRQ_NOREQUEST);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun arch_initcall(bast_irq_init);
138