1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun #include <linux/init.h>
3*4882a593Smuzhiyun #include <linux/list.h>
4*4882a593Smuzhiyun #include <linux/io.h>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <asm/mach/irq.h>
7*4882a593Smuzhiyun #include <asm/hardware/iomd.h>
8*4882a593Smuzhiyun #include <asm/irq.h>
9*4882a593Smuzhiyun #include <asm/fiq.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun // These are offsets from the stat register for each IRQ bank
12*4882a593Smuzhiyun #define STAT 0x00
13*4882a593Smuzhiyun #define REQ 0x04
14*4882a593Smuzhiyun #define CLR 0x04
15*4882a593Smuzhiyun #define MASK 0x08
16*4882a593Smuzhiyun
iomd_get_base(struct irq_data * d)17*4882a593Smuzhiyun static void __iomem *iomd_get_base(struct irq_data *d)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun void *cd = irq_data_get_irq_chip_data(d);
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun return (void __iomem *)(unsigned long)cd;
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
iomd_set_base_mask(unsigned int irq,void __iomem * base,u32 mask)24*4882a593Smuzhiyun static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct irq_data *d = irq_get_irq_data(irq);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun d->mask = mask;
29*4882a593Smuzhiyun irq_set_chip_data(irq, (void *)(unsigned long)base);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
iomd_irq_mask_ack(struct irq_data * d)32*4882a593Smuzhiyun static void iomd_irq_mask_ack(struct irq_data *d)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun void __iomem *base = iomd_get_base(d);
35*4882a593Smuzhiyun unsigned int val, mask = d->mask;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun val = readb(base + MASK);
38*4882a593Smuzhiyun writeb(val & ~mask, base + MASK);
39*4882a593Smuzhiyun writeb(mask, base + CLR);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
iomd_irq_mask(struct irq_data * d)42*4882a593Smuzhiyun static void iomd_irq_mask(struct irq_data *d)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun void __iomem *base = iomd_get_base(d);
45*4882a593Smuzhiyun unsigned int val, mask = d->mask;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun val = readb(base + MASK);
48*4882a593Smuzhiyun writeb(val & ~mask, base + MASK);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
iomd_irq_unmask(struct irq_data * d)51*4882a593Smuzhiyun static void iomd_irq_unmask(struct irq_data *d)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun void __iomem *base = iomd_get_base(d);
54*4882a593Smuzhiyun unsigned int val, mask = d->mask;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun val = readb(base + MASK);
57*4882a593Smuzhiyun writeb(val | mask, base + MASK);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static struct irq_chip iomd_chip_clr = {
61*4882a593Smuzhiyun .irq_mask_ack = iomd_irq_mask_ack,
62*4882a593Smuzhiyun .irq_mask = iomd_irq_mask,
63*4882a593Smuzhiyun .irq_unmask = iomd_irq_unmask,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static struct irq_chip iomd_chip_noclr = {
67*4882a593Smuzhiyun .irq_mask = iomd_irq_mask,
68*4882a593Smuzhiyun .irq_unmask = iomd_irq_unmask,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
72*4882a593Smuzhiyun
rpc_init_irq(void)73*4882a593Smuzhiyun void __init rpc_init_irq(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun unsigned int irq, clr, set;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun iomd_writeb(0, IOMD_IRQMASKA);
78*4882a593Smuzhiyun iomd_writeb(0, IOMD_IRQMASKB);
79*4882a593Smuzhiyun iomd_writeb(0, IOMD_FIQMASK);
80*4882a593Smuzhiyun iomd_writeb(0, IOMD_DMAMASK);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun set_fiq_handler(&rpc_default_fiq_start,
83*4882a593Smuzhiyun &rpc_default_fiq_end - &rpc_default_fiq_start);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun for (irq = 0; irq < NR_IRQS; irq++) {
86*4882a593Smuzhiyun clr = IRQ_NOREQUEST;
87*4882a593Smuzhiyun set = 0;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (irq <= 6 || (irq >= 9 && irq <= 15))
90*4882a593Smuzhiyun clr |= IRQ_NOPROBE;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (irq == 21 || (irq >= 16 && irq <= 19) ||
93*4882a593Smuzhiyun irq == IRQ_KEYBOARDTX)
94*4882a593Smuzhiyun set |= IRQ_NOAUTOEN;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun switch (irq) {
97*4882a593Smuzhiyun case 0 ... 7:
98*4882a593Smuzhiyun irq_set_chip_and_handler(irq, &iomd_chip_clr,
99*4882a593Smuzhiyun handle_level_irq);
100*4882a593Smuzhiyun irq_modify_status(irq, clr, set);
101*4882a593Smuzhiyun iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA,
102*4882a593Smuzhiyun BIT(irq));
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun case 8 ... 15:
106*4882a593Smuzhiyun irq_set_chip_and_handler(irq, &iomd_chip_noclr,
107*4882a593Smuzhiyun handle_level_irq);
108*4882a593Smuzhiyun irq_modify_status(irq, clr, set);
109*4882a593Smuzhiyun iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB,
110*4882a593Smuzhiyun BIT(irq - 8));
111*4882a593Smuzhiyun break;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun case 16 ... 21:
114*4882a593Smuzhiyun irq_set_chip_and_handler(irq, &iomd_chip_noclr,
115*4882a593Smuzhiyun handle_level_irq);
116*4882a593Smuzhiyun irq_modify_status(irq, clr, set);
117*4882a593Smuzhiyun iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT,
118*4882a593Smuzhiyun BIT(irq - 16));
119*4882a593Smuzhiyun break;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun case 64 ... 71:
122*4882a593Smuzhiyun irq_set_chip(irq, &iomd_chip_noclr);
123*4882a593Smuzhiyun irq_modify_status(irq, clr, set);
124*4882a593Smuzhiyun iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT,
125*4882a593Smuzhiyun BIT(irq - 64));
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun init_FIQ(FIQ_START);
131*4882a593Smuzhiyun }
132