1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-rpc/include/mach/hardware.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1996-1999 Russell King. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file contains the hardware definitions of the RiscPC series machines. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_HARDWARE_H 10*4882a593Smuzhiyun #define __ASM_ARCH_HARDWARE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <mach/memory.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * What hardware must be present 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define HAS_IOMD 18*4882a593Smuzhiyun #define HAS_VIDC20 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Hardware addresses of major areas. 21*4882a593Smuzhiyun * *_START is the physical address 22*4882a593Smuzhiyun * *_SIZE is the size of the region 23*4882a593Smuzhiyun * *_BASE is the virtual address 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define RPC_RAM_SIZE 0x10000000 26*4882a593Smuzhiyun #define RPC_RAM_START 0x10000000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define EASI_SIZE 0x08000000 /* EASI I/O */ 29*4882a593Smuzhiyun #define EASI_START 0x08000000 30*4882a593Smuzhiyun #define EASI_BASE IOMEM(0xe5000000) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define IO_START 0x03000000 /* I/O */ 33*4882a593Smuzhiyun #define IO_SIZE 0x01000000 34*4882a593Smuzhiyun #define IO_BASE IOMEM(0xe0000000) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define SCREEN_START 0x02000000 /* VRAM */ 37*4882a593Smuzhiyun #define SCREEN_END 0xdfc00000 38*4882a593Smuzhiyun #define SCREEN_BASE 0xdf800000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define UNCACHEABLE_ADDR (FLUSH_BASE + 0x10000) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * IO Addresses 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define ECARD_EASI_BASE (EASI_BASE) 46*4882a593Smuzhiyun #define VIDC_BASE (IO_BASE + 0x00400000) 47*4882a593Smuzhiyun #define EXPMASK_BASE (IO_BASE + 0x00360000) 48*4882a593Smuzhiyun #define ECARD_IOC4_BASE (IO_BASE + 0x00270000) 49*4882a593Smuzhiyun #define ECARD_IOC_BASE (IO_BASE + 0x00240000) 50*4882a593Smuzhiyun #define IOMD_BASE (IO_BASE + 0x00200000) 51*4882a593Smuzhiyun #define IOC_BASE (IO_BASE + 0x00200000) 52*4882a593Smuzhiyun #define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000) 53*4882a593Smuzhiyun #define FLOPPYDMA_BASE (IO_BASE + 0x0002a000) 54*4882a593Smuzhiyun #define PCIO_BASE (IO_BASE + 0x00010000) 55*4882a593Smuzhiyun #define ECARD_MEMC_BASE (IO_BASE + 0x00000000) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define vidc_writel(val) __raw_writel(val, VIDC_BASE) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define NETSLOT_BASE 0x0302b000 60*4882a593Smuzhiyun #define NETSLOT_SIZE 0x00001000 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define PODSLOT_IOC0_BASE 0x03240000 63*4882a593Smuzhiyun #define PODSLOT_IOC4_BASE 0x03270000 64*4882a593Smuzhiyun #define PODSLOT_IOC_SIZE (1 << 14) 65*4882a593Smuzhiyun #define PODSLOT_MEMC_BASE 0x03000000 66*4882a593Smuzhiyun #define PODSLOT_MEMC_SIZE (1 << 14) 67*4882a593Smuzhiyun #define PODSLOT_EASI_BASE 0x08000000 68*4882a593Smuzhiyun #define PODSLOT_EASI_SIZE (1 << 24) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define EXPMASK_STATUS (EXPMASK_BASE + 0x00) 71*4882a593Smuzhiyun #define EXPMASK_ENABLE (EXPMASK_BASE + 0x04) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif 74