1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Device Tree support for Rockchip SoCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013 MundoReader S.L.
6*4882a593Smuzhiyun * Author: Heiko Stuebner <heiko@sntech.de>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/of_clk.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/irqchip.h>
15*4882a593Smuzhiyun #include <linux/clocksource.h>
16*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <asm/mach/arch.h>
19*4882a593Smuzhiyun #include <asm/mach/map.h>
20*4882a593Smuzhiyun #include <asm/hardware/cache-l2x0.h>
21*4882a593Smuzhiyun #include "core.h"
22*4882a593Smuzhiyun #include "pm.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define RK3288_TIMER6_7_PHYS 0xff810000
25*4882a593Smuzhiyun
rockchip_timer_init(void)26*4882a593Smuzhiyun static void __init rockchip_timer_init(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun if (of_machine_is_compatible("rockchip,rk3288")) {
29*4882a593Smuzhiyun void __iomem *reg_base;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Most/all uboot versions for rk3288 don't enable timer7
33*4882a593Smuzhiyun * which is needed for the architected timer to work.
34*4882a593Smuzhiyun * So make sure it is running during early boot.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
37*4882a593Smuzhiyun if (reg_base) {
38*4882a593Smuzhiyun writel(0, reg_base + 0x30);
39*4882a593Smuzhiyun writel(0xffffffff, reg_base + 0x20);
40*4882a593Smuzhiyun writel(0xffffffff, reg_base + 0x24);
41*4882a593Smuzhiyun writel(1, reg_base + 0x30);
42*4882a593Smuzhiyun dsb();
43*4882a593Smuzhiyun iounmap(reg_base);
44*4882a593Smuzhiyun } else {
45*4882a593Smuzhiyun pr_err("rockchip: could not map timer7 registers\n");
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun of_clk_init(NULL);
50*4882a593Smuzhiyun timer_probe();
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
rockchip_dt_init(void)53*4882a593Smuzhiyun static void __init rockchip_dt_init(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun rockchip_suspend_init();
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static const char * const rockchip_board_dt_compat[] = {
59*4882a593Smuzhiyun "rockchip,rk2928",
60*4882a593Smuzhiyun "rockchip,rk3066a",
61*4882a593Smuzhiyun "rockchip,rk3066b",
62*4882a593Smuzhiyun "rockchip,rk3188",
63*4882a593Smuzhiyun "rockchip,rk3228",
64*4882a593Smuzhiyun "rockchip,rk3288",
65*4882a593Smuzhiyun "rockchip,rv1106",
66*4882a593Smuzhiyun "rockchip,rv1108",
67*4882a593Smuzhiyun NULL,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun DT_MACHINE_START(ROCKCHIP_DT, "Rockchip (Device Tree)")
71*4882a593Smuzhiyun .l2c_aux_val = 0,
72*4882a593Smuzhiyun .l2c_aux_mask = ~0,
73*4882a593Smuzhiyun .init_time = rockchip_timer_init,
74*4882a593Smuzhiyun .dt_compat = rockchip_board_dt_compat,
75*4882a593Smuzhiyun .init_machine = rockchip_dt_init,
76*4882a593Smuzhiyun MACHINE_END
77