1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "rkpm_helpers.h"
9*4882a593Smuzhiyun #include "rkpm_uart.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define UART_DEFAULT_BAUDRATE 115200
12*4882a593Smuzhiyun
rkpm_uart_debug_init(void __iomem * base,unsigned int uart_clk,unsigned int baud_rate)13*4882a593Smuzhiyun void rkpm_uart_debug_init(void __iomem *base,
14*4882a593Smuzhiyun unsigned int uart_clk,
15*4882a593Smuzhiyun unsigned int baud_rate)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun u32 uart_dll, uart_dlh;
18*4882a593Smuzhiyun u32 div;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun if (!base || !uart_clk || !baud_rate)
21*4882a593Smuzhiyun return;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun div = uart_clk / baud_rate / 16;
24*4882a593Smuzhiyun uart_dll = div & 0xff;
25*4882a593Smuzhiyun uart_dlh = (div >> 8) & 0xff;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Reset uart */
28*4882a593Smuzhiyun writel_relaxed(XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET,
29*4882a593Smuzhiyun base + UARTSRR);
30*4882a593Smuzhiyun rkpm_raw_udelay(10);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun writel_relaxed(DIAGNOSTIC_MODE, base + UARTMCR);
33*4882a593Smuzhiyun writel_relaxed(0x83, base + UARTLCR);
34*4882a593Smuzhiyun writel_relaxed(uart_dll, base + UARTDLL);
35*4882a593Smuzhiyun writel_relaxed(uart_dlh, base + UARTDLLM);
36*4882a593Smuzhiyun writel_relaxed(0x03, base + UARTLCR);
37*4882a593Smuzhiyun writel_relaxed(0x01, base + UARTIER);
38*4882a593Smuzhiyun writel_relaxed(UARTFCR_FIFOEN, base + UARTFCR);
39*4882a593Smuzhiyun writel_relaxed(0, base + UARTMCR);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
rkpm_uart_debug_save(void __iomem * base,struct uart_debug_ctx * ctx)42*4882a593Smuzhiyun void rkpm_uart_debug_save(void __iomem *base,
43*4882a593Smuzhiyun struct uart_debug_ctx *ctx)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun u32 wait_cnt = 50000;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun while ((readl_relaxed(base + UARTUSR) & UARTUSR_BUSY) &&
48*4882a593Smuzhiyun --wait_cnt)
49*4882a593Smuzhiyun rkpm_raw_udelay(10);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Uart error! Unlikely to reach here */
52*4882a593Smuzhiyun if (wait_cnt == 0)
53*4882a593Smuzhiyun rkpm_uart_debug_init(base, 24000000, UART_DEFAULT_BAUDRATE);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun ctx->uart_lcr = readl_relaxed(base + UARTLCR);
56*4882a593Smuzhiyun ctx->uart_ier = readl_relaxed(base + UARTIER);
57*4882a593Smuzhiyun ctx->uart_mcr = readl_relaxed(base + UARTMCR);
58*4882a593Smuzhiyun writel_relaxed(ctx->uart_lcr | UARTLCR_DLAB, base + UARTLCR);
59*4882a593Smuzhiyun ctx->uart_dll = readl_relaxed(base + UARTDLL);
60*4882a593Smuzhiyun ctx->uart_dlh = readl_relaxed(base + UARTDLLM);
61*4882a593Smuzhiyun writel_relaxed(ctx->uart_lcr, base + UARTLCR);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
rkpm_uart_debug_restore(void __iomem * base,struct uart_debug_ctx * ctx)64*4882a593Smuzhiyun void rkpm_uart_debug_restore(void __iomem *base,
65*4882a593Smuzhiyun struct uart_debug_ctx *ctx)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun u32 uart_lcr;
68*4882a593Smuzhiyun u32 wait_cnt = 50000;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun while ((readl_relaxed(base + UARTUSR) & UARTUSR_BUSY) &&
71*4882a593Smuzhiyun --wait_cnt)
72*4882a593Smuzhiyun rkpm_raw_udelay(10);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun writel_relaxed(XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET,
75*4882a593Smuzhiyun base + UARTSRR);
76*4882a593Smuzhiyun rkpm_raw_udelay(10);
77*4882a593Smuzhiyun uart_lcr = readl_relaxed(base + UARTLCR);
78*4882a593Smuzhiyun writel_relaxed(DIAGNOSTIC_MODE, base + UARTMCR);
79*4882a593Smuzhiyun writel_relaxed(uart_lcr | UARTLCR_DLAB, base + UARTLCR);
80*4882a593Smuzhiyun writel_relaxed(ctx->uart_dll, base + UARTDLL);
81*4882a593Smuzhiyun writel_relaxed(ctx->uart_dlh, base + UARTDLLM);
82*4882a593Smuzhiyun writel_relaxed(ctx->uart_lcr, base + UARTLCR);
83*4882a593Smuzhiyun writel_relaxed(ctx->uart_ier, base + UARTIER);
84*4882a593Smuzhiyun writel_relaxed(UARTFCR_FIFOEN, base + UARTFCR);
85*4882a593Smuzhiyun writel_relaxed(ctx->uart_mcr, base + UARTMCR);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
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