1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef RKPM_HELPERS_H 7*4882a593Smuzhiyun #define RKPM_HELPERS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define REG_MSK_SHIFT 16 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef BIT 12*4882a593Smuzhiyun #define BIT(nr) (1U << (nr)) 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef WMSK_BIT 16*4882a593Smuzhiyun #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* set one bit with write mask */ 20*4882a593Smuzhiyun #ifndef BIT_WITH_WMSK 21*4882a593Smuzhiyun #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef BITS_SHIFT 25*4882a593Smuzhiyun #define BITS_SHIFT(bits, shift) ((bits) << (shift)) 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #ifndef BITS_WMSK 29*4882a593Smuzhiyun #define BITS_WMSK(msk, shift) \ 30*4882a593Smuzhiyun ((msk) << ((shift) + REG_MSK_SHIFT)) 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #ifndef BITS_WITH_WMASK 34*4882a593Smuzhiyun #define BITS_WITH_WMASK(bits, msk, shift) \ 35*4882a593Smuzhiyun (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, ((shift) + REG_MSK_SHIFT))) 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #ifndef BIT_SET_WMSK 39*4882a593Smuzhiyun #define BIT_SET_WMSK(nr) BIT_WITH_WMSK(nr) 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #ifndef BIT_CLR_WMSK 43*4882a593Smuzhiyun #define BIT_CLR_WMSK(nr) WMSK_BIT(nr) 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #ifndef WITH_16BITS_WMSK 47*4882a593Smuzhiyun #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define REG_REGION(_start, _end, _stride, _base, _wmsk) \ 51*4882a593Smuzhiyun .start = (_start), \ 52*4882a593Smuzhiyun .end = (_end), \ 53*4882a593Smuzhiyun .stride = (_stride), \ 54*4882a593Smuzhiyun .wmsk = (_wmsk), \ 55*4882a593Smuzhiyun .base = (_base), 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct reg_region { 58*4882a593Smuzhiyun void __iomem **base; 59*4882a593Smuzhiyun u32 start; 60*4882a593Smuzhiyun u32 end; 61*4882a593Smuzhiyun u32 stride; 62*4882a593Smuzhiyun u32 wmsk; 63*4882a593Smuzhiyun u32 *buf; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun void rkpm_alloc_region_mem(struct reg_region *rgns, u32 rgn_num); 67*4882a593Smuzhiyun void rkpm_region_mem_init(u32 size); 68*4882a593Smuzhiyun void rkpm_reg_rgn_save(struct reg_region *rgns, u32 rgn_num); 69*4882a593Smuzhiyun void rkpm_reg_rgn_restore(struct reg_region *rgns, u32 rgn_num); 70*4882a593Smuzhiyun void rkpm_reg_rgn_restore_reverse(struct reg_region *rgns, u32 rgn_num); 71*4882a593Smuzhiyun void rkpm_dump_reg_rgns(struct reg_region *rgns, u32 rgn_num); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun void rkpm_printch(int c); 74*4882a593Smuzhiyun void rkpm_printstr(const char *s); 75*4882a593Smuzhiyun void rkpm_printhex(u32 hex); 76*4882a593Smuzhiyun void rkpm_printdec(int dec); 77*4882a593Smuzhiyun void rkpm_regs_dump(void __iomem *base, 78*4882a593Smuzhiyun u32 start_offset, 79*4882a593Smuzhiyun u32 end_offset, 80*4882a593Smuzhiyun u32 stride); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun void rkpm_raw_udelay(int us); 83*4882a593Smuzhiyun #endif 84