1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun * Author: Tony Xie <tony.xie@rock-chips.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __MACH_ROCKCHIP_PM_H
8*4882a593Smuzhiyun #define __MACH_ROCKCHIP_PM_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun extern unsigned long rkpm_bootdata_cpusp;
11*4882a593Smuzhiyun extern unsigned long rkpm_bootdata_cpu_code;
12*4882a593Smuzhiyun extern unsigned long rkpm_bootdata_l2ctlr_f;
13*4882a593Smuzhiyun extern unsigned long rkpm_bootdata_l2ctlr;
14*4882a593Smuzhiyun extern unsigned long rkpm_bootdata_ddr_code;
15*4882a593Smuzhiyun extern unsigned long rkpm_bootdata_ddr_data;
16*4882a593Smuzhiyun extern unsigned long rk3288_bootram_sz;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun void rockchip_slp_cpu_resume(void);
19*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
20*4882a593Smuzhiyun void __init rockchip_suspend_init(void);
21*4882a593Smuzhiyun #else
rockchip_suspend_init(void)22*4882a593Smuzhiyun static inline void rockchip_suspend_init(void)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /****** following is rk3288 defined **********/
28*4882a593Smuzhiyun #define RK3288_PMU_WAKEUP_CFG0 0x00
29*4882a593Smuzhiyun #define RK3288_PMU_WAKEUP_CFG1 0x04
30*4882a593Smuzhiyun #define RK3288_PMU_PWRMODE_CON 0x18
31*4882a593Smuzhiyun #define RK3288_PMU_OSC_CNT 0x20
32*4882a593Smuzhiyun #define RK3288_PMU_PLL_CNT 0x24
33*4882a593Smuzhiyun #define RK3288_PMU_STABL_CNT 0x28
34*4882a593Smuzhiyun #define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
35*4882a593Smuzhiyun #define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
36*4882a593Smuzhiyun #define RK3288_PMU_CORE_PWRDWN_CNT 0x34
37*4882a593Smuzhiyun #define RK3288_PMU_CORE_PWRUP_CNT 0x38
38*4882a593Smuzhiyun #define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
39*4882a593Smuzhiyun #define RK3288_PMU_GPU_PWRUP_CNT 0x40
40*4882a593Smuzhiyun #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
41*4882a593Smuzhiyun #define RK3288_PMU_PWRMODE_CON1 0x90
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON0 (0x0000)
44*4882a593Smuzhiyun #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
45*4882a593Smuzhiyun #define SGRF_PCLK_WDT_GATE BIT(6)
46*4882a593Smuzhiyun #define SGRF_PCLK_WDT_GATE_WRITE BIT(22)
47*4882a593Smuzhiyun #define SGRF_FAST_BOOT_EN BIT(8)
48*4882a593Smuzhiyun #define SGRF_FAST_BOOT_EN_WRITE BIT(24)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define RK3288_SGRF_CPU_CON0 (0x40)
51*4882a593Smuzhiyun #define SGRF_DAPDEVICEEN BIT(0)
52*4882a593Smuzhiyun #define SGRF_DAPDEVICEEN_WRITE BIT(16)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* PMU_WAKEUP_CFG1 bits */
55*4882a593Smuzhiyun #define PMU_ARMINT_WAKEUP_EN BIT(0)
56*4882a593Smuzhiyun #define PMU_GPIOINT_WAKEUP_EN BIT(3)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun enum rk3288_pwr_mode_con {
59*4882a593Smuzhiyun PMU_PWR_MODE_EN = 0,
60*4882a593Smuzhiyun PMU_CLK_CORE_SRC_GATE_EN,
61*4882a593Smuzhiyun PMU_GLOBAL_INT_DISABLE,
62*4882a593Smuzhiyun PMU_L2FLUSH_EN,
63*4882a593Smuzhiyun PMU_BUS_PD_EN,
64*4882a593Smuzhiyun PMU_A12_0_PD_EN,
65*4882a593Smuzhiyun PMU_SCU_EN,
66*4882a593Smuzhiyun PMU_PLL_PD_EN,
67*4882a593Smuzhiyun PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
68*4882a593Smuzhiyun PMU_PWROFF_COMB,
69*4882a593Smuzhiyun PMU_ALIVE_USE_LF,
70*4882a593Smuzhiyun PMU_PMU_USE_LF,
71*4882a593Smuzhiyun PMU_OSC_24M_DIS,
72*4882a593Smuzhiyun PMU_INPUT_CLAMP_EN,
73*4882a593Smuzhiyun PMU_WAKEUP_RESET_EN,
74*4882a593Smuzhiyun PMU_SREF0_ENTER_EN,
75*4882a593Smuzhiyun PMU_SREF1_ENTER_EN,
76*4882a593Smuzhiyun PMU_DDR0IO_RET_EN,
77*4882a593Smuzhiyun PMU_DDR1IO_RET_EN,
78*4882a593Smuzhiyun PMU_DDR0_GATING_EN,
79*4882a593Smuzhiyun PMU_DDR1_GATING_EN,
80*4882a593Smuzhiyun PMU_DDR0IO_RET_DE_REQ,
81*4882a593Smuzhiyun PMU_DDR1IO_RET_DE_REQ
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun enum rk3288_pwr_mode_con1 {
85*4882a593Smuzhiyun PMU_CLR_BUS = 0,
86*4882a593Smuzhiyun PMU_CLR_CORE,
87*4882a593Smuzhiyun PMU_CLR_CPUP,
88*4882a593Smuzhiyun PMU_CLR_ALIVE,
89*4882a593Smuzhiyun PMU_CLR_DMA,
90*4882a593Smuzhiyun PMU_CLR_PERI,
91*4882a593Smuzhiyun PMU_CLR_GPU,
92*4882a593Smuzhiyun PMU_CLR_VIDEO,
93*4882a593Smuzhiyun PMU_CLR_HEVC,
94*4882a593Smuzhiyun PMU_CLR_VIO,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #endif /* __MACH_ROCKCHIP_PM_H */
98