1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-pxa/include/mach/zeus.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: David Vrabel 6*4882a593Smuzhiyun * Created: Sept 28, 2005 7*4882a593Smuzhiyun * Copyright: Arcom Control Systems Ltd. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Maintained by: Marc Zyngier <maz@misterjones.org> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _MACH_ZEUS_H 13*4882a593Smuzhiyun #define _MACH_ZEUS_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ZEUS_NR_IRQS (IRQ_BOARD_START + 48) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Physical addresses */ 18*4882a593Smuzhiyun #define ZEUS_FLASH_PHYS PXA_CS0_PHYS 19*4882a593Smuzhiyun #define ZEUS_ETH0_PHYS PXA_CS1_PHYS 20*4882a593Smuzhiyun #define ZEUS_ETH1_PHYS PXA_CS2_PHYS 21*4882a593Smuzhiyun #define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000) 22*4882a593Smuzhiyun #define ZEUS_SRAM_PHYS PXA_CS5_PHYS 23*4882a593Smuzhiyun #define ZEUS_PC104IO_PHYS (0x30000000) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000) 26*4882a593Smuzhiyun #define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000) 27*4882a593Smuzhiyun #define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000) 28*4882a593Smuzhiyun #define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* GPIOs */ 31*4882a593Smuzhiyun #define ZEUS_AC97_GPIO 0 32*4882a593Smuzhiyun #define ZEUS_WAKEUP_GPIO 1 33*4882a593Smuzhiyun #define ZEUS_UARTA_GPIO 9 34*4882a593Smuzhiyun #define ZEUS_UARTB_GPIO 10 35*4882a593Smuzhiyun #define ZEUS_UARTC_GPIO 12 36*4882a593Smuzhiyun #define ZEUS_UARTD_GPIO 11 37*4882a593Smuzhiyun #define ZEUS_ETH0_GPIO 14 38*4882a593Smuzhiyun #define ZEUS_ISA_GPIO 17 39*4882a593Smuzhiyun #define ZEUS_BKLEN_GPIO 19 40*4882a593Smuzhiyun #define ZEUS_USB2_PWREN_GPIO 22 41*4882a593Smuzhiyun #define ZEUS_PTT_GPIO 27 42*4882a593Smuzhiyun #define ZEUS_CF_CD_GPIO 35 43*4882a593Smuzhiyun #define ZEUS_MMC_WP_GPIO 52 44*4882a593Smuzhiyun #define ZEUS_MMC_CD_GPIO 53 45*4882a593Smuzhiyun #define ZEUS_EXTGPIO_GPIO 91 46*4882a593Smuzhiyun #define ZEUS_CF_PWEN_GPIO 97 47*4882a593Smuzhiyun #define ZEUS_CF_RDY_GPIO 99 48*4882a593Smuzhiyun #define ZEUS_LCD_EN_GPIO 101 49*4882a593Smuzhiyun #define ZEUS_ETH1_GPIO 113 50*4882a593Smuzhiyun #define ZEUS_CAN_GPIO 116 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define ZEUS_EXT0_GPIO_BASE 128 53*4882a593Smuzhiyun #define ZEUS_EXT1_GPIO_BASE 160 54*4882a593Smuzhiyun #define ZEUS_USER_GPIO_BASE 192 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x)) 57*4882a593Smuzhiyun #define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) 58*4882a593Smuzhiyun #define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * CPLD registers: 64*4882a593Smuzhiyun * Only 4 registers, but spread over a 32MB address space. 65*4882a593Smuzhiyun * Be gentle, and remap that over 32kB... 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define ZEUS_CPLD IOMEM(0xf0000000) 69*4882a593Smuzhiyun #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) 70*4882a593Smuzhiyun #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) 71*4882a593Smuzhiyun #define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* CPLD register bits */ 74*4882a593Smuzhiyun #define ZEUS_CPLD_CONTROL_CF_RST 0x01 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define ZEUS_PC104IO IOMEM(0xf1000000) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define ZEUS_SRAM_SIZE (256 * 1024) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun 83