1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-pxa/include/mach/viper.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Ian Campbell 6*4882a593Smuzhiyun * Created: Feb 03, 2003 7*4882a593Smuzhiyun * Copyright: Arcom Control Systems. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Maintained by Marc Zyngier <maz@misterjones.org> 10*4882a593Smuzhiyun * <marc.zyngier@altran.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Created based on lubbock.h: 13*4882a593Smuzhiyun * Author: Nicolas Pitre 14*4882a593Smuzhiyun * Created: Jun 15, 2001 15*4882a593Smuzhiyun * Copyright: MontaVista Software Inc. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef ARCH_VIPER_H 19*4882a593Smuzhiyun #define ARCH_VIPER_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define VIPER_BOOT_PHYS PXA_CS0_PHYS 22*4882a593Smuzhiyun #define VIPER_FLASH_PHYS PXA_CS1_PHYS 23*4882a593Smuzhiyun #define VIPER_ETH_PHYS PXA_CS2_PHYS 24*4882a593Smuzhiyun #define VIPER_USB_PHYS PXA_CS3_PHYS 25*4882a593Smuzhiyun #define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS 26*4882a593Smuzhiyun #define VIPER_CPLD_PHYS PXA_CS5_PHYS 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define VIPER_CPLD_BASE (0xf0000000) 29*4882a593Smuzhiyun #define VIPER_PC104IO_BASE (0xf1000000) 30*4882a593Smuzhiyun #define VIPER_USB_BASE (0xf1800000) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define VIPER_ETH_GPIO (0) 33*4882a593Smuzhiyun #define VIPER_CPLD_GPIO (1) 34*4882a593Smuzhiyun #define VIPER_USB_GPIO (2) 35*4882a593Smuzhiyun #define VIPER_UARTA_GPIO (4) 36*4882a593Smuzhiyun #define VIPER_UARTB_GPIO (3) 37*4882a593Smuzhiyun #define VIPER_CF_CD_GPIO (32) 38*4882a593Smuzhiyun #define VIPER_CF_RDY_GPIO (8) 39*4882a593Smuzhiyun #define VIPER_BCKLIGHT_EN_GPIO (9) 40*4882a593Smuzhiyun #define VIPER_LCD_EN_GPIO (10) 41*4882a593Smuzhiyun #define VIPER_PSU_DATA_GPIO (6) 42*4882a593Smuzhiyun #define VIPER_PSU_CLK_GPIO (11) 43*4882a593Smuzhiyun #define VIPER_UART_SHDN_GPIO (12) 44*4882a593Smuzhiyun #define VIPER_BRIGHTNESS_GPIO (16) 45*4882a593Smuzhiyun #define VIPER_PSU_nCS_LD_GPIO (19) 46*4882a593Smuzhiyun #define VIPER_UPS_GPIO (20) 47*4882a593Smuzhiyun #define VIPER_CF_POWER_GPIO (82) 48*4882a593Smuzhiyun #define VIPER_TPM_I2C_SDA_GPIO (26) 49*4882a593Smuzhiyun #define VIPER_TPM_I2C_SCL_GPIO (27) 50*4882a593Smuzhiyun #define VIPER_RTC_I2C_SDA_GPIO (83) 51*4882a593Smuzhiyun #define VIPER_RTC_I2C_SCL_GPIO (84) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE) 54*4882a593Smuzhiyun #define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 57*4882a593Smuzhiyun # define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x))) 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* board level registers in the CPLD: (offsets from CPLD_BASE) ... */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* ... Physical addresses */ 63*4882a593Smuzhiyun #define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000) 64*4882a593Smuzhiyun #define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002) 65*4882a593Smuzhiyun #define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004) 66*4882a593Smuzhiyun #define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006) 67*4882a593Smuzhiyun #define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010) 68*4882a593Smuzhiyun #define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000) 69*4882a593Smuzhiyun #define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* ... Virtual addresses */ 72*4882a593Smuzhiyun #define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS) 73*4882a593Smuzhiyun #define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS) 74*4882a593Smuzhiyun #define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS) 75*4882a593Smuzhiyun #define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Decode VIPER_VERSION register */ 78*4882a593Smuzhiyun #define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7) 79*4882a593Smuzhiyun #define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3) 80*4882a593Smuzhiyun #define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Interrupt and Configuration Register (VIPER_ICR) */ 83*4882a593Smuzhiyun /* This is a write only register. Only CF_RST is used under Linux */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define VIPER_ICR_RETRIG (1 << 0) 86*4882a593Smuzhiyun #define VIPER_ICR_AUTO_CLR (1 << 1) 87*4882a593Smuzhiyun #define VIPER_ICR_R_DIS (1 << 2) 88*4882a593Smuzhiyun #define VIPER_ICR_CF_RST (1 << 3) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif 91*4882a593Smuzhiyun 92