xref: /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/viper.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  linux/arch/arm/mach-pxa/viper.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Support for the Arcom VIPER SBC.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *  Author:	Ian Campbell
8*4882a593Smuzhiyun  *  Created:    Feb 03, 2003
9*4882a593Smuzhiyun  *  Copyright:  Arcom Control Systems
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  *  Maintained by Marc Zyngier <maz@misterjones.org>
12*4882a593Smuzhiyun  *                             <marc.zyngier@altran.com>
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * Based on lubbock.c:
15*4882a593Smuzhiyun  *  Author:	Nicolas Pitre
16*4882a593Smuzhiyun  *  Created:	Jun 15, 2001
17*4882a593Smuzhiyun  *  Copyright:	MontaVista Software Inc.
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/types.h>
21*4882a593Smuzhiyun #include <linux/memory.h>
22*4882a593Smuzhiyun #include <linux/cpu.h>
23*4882a593Smuzhiyun #include <linux/cpufreq.h>
24*4882a593Smuzhiyun #include <linux/delay.h>
25*4882a593Smuzhiyun #include <linux/fs.h>
26*4882a593Smuzhiyun #include <linux/init.h>
27*4882a593Smuzhiyun #include <linux/slab.h>
28*4882a593Smuzhiyun #include <linux/interrupt.h>
29*4882a593Smuzhiyun #include <linux/major.h>
30*4882a593Smuzhiyun #include <linux/module.h>
31*4882a593Smuzhiyun #include <linux/pm.h>
32*4882a593Smuzhiyun #include <linux/sched.h>
33*4882a593Smuzhiyun #include <linux/gpio.h>
34*4882a593Smuzhiyun #include <linux/jiffies.h>
35*4882a593Smuzhiyun #include <linux/platform_data/i2c-gpio.h>
36*4882a593Smuzhiyun #include <linux/gpio/machine.h>
37*4882a593Smuzhiyun #include <linux/platform_data/i2c-pxa.h>
38*4882a593Smuzhiyun #include <linux/serial_8250.h>
39*4882a593Smuzhiyun #include <linux/smc91x.h>
40*4882a593Smuzhiyun #include <linux/pwm.h>
41*4882a593Smuzhiyun #include <linux/pwm_backlight.h>
42*4882a593Smuzhiyun #include <linux/usb/isp116x.h>
43*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
44*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
45*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
46*4882a593Smuzhiyun #include <linux/syscore_ops.h>
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #include "pxa25x.h"
49*4882a593Smuzhiyun #include <mach/audio.h>
50*4882a593Smuzhiyun #include <linux/platform_data/video-pxafb.h>
51*4882a593Smuzhiyun #include <mach/regs-uart.h>
52*4882a593Smuzhiyun #include <linux/platform_data/pcmcia-pxa2xx_viper.h>
53*4882a593Smuzhiyun #include "viper.h"
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #include <asm/setup.h>
56*4882a593Smuzhiyun #include <asm/mach-types.h>
57*4882a593Smuzhiyun #include <asm/irq.h>
58*4882a593Smuzhiyun #include <linux/sizes.h>
59*4882a593Smuzhiyun #include <asm/system_info.h>
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #include <asm/mach/arch.h>
62*4882a593Smuzhiyun #include <asm/mach/map.h>
63*4882a593Smuzhiyun #include <asm/mach/irq.h>
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #include "generic.h"
66*4882a593Smuzhiyun #include "devices.h"
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun static unsigned int icr;
69*4882a593Smuzhiyun 
viper_icr_set_bit(unsigned int bit)70*4882a593Smuzhiyun static void viper_icr_set_bit(unsigned int bit)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	icr |= bit;
73*4882a593Smuzhiyun 	VIPER_ICR = icr;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
viper_icr_clear_bit(unsigned int bit)76*4882a593Smuzhiyun static void viper_icr_clear_bit(unsigned int bit)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	icr &= ~bit;
79*4882a593Smuzhiyun 	VIPER_ICR = icr;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /* This function is used from the pcmcia module to reset the CF */
viper_cf_reset(int state)83*4882a593Smuzhiyun static void viper_cf_reset(int state)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	if (state)
86*4882a593Smuzhiyun 		viper_icr_set_bit(VIPER_ICR_CF_RST);
87*4882a593Smuzhiyun 	else
88*4882a593Smuzhiyun 		viper_icr_clear_bit(VIPER_ICR_CF_RST);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun static struct arcom_pcmcia_pdata viper_pcmcia_info = {
92*4882a593Smuzhiyun 	.cd_gpio	= VIPER_CF_CD_GPIO,
93*4882a593Smuzhiyun 	.rdy_gpio	= VIPER_CF_RDY_GPIO,
94*4882a593Smuzhiyun 	.pwr_gpio	= VIPER_CF_POWER_GPIO,
95*4882a593Smuzhiyun 	.reset		= viper_cf_reset,
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun static struct platform_device viper_pcmcia_device = {
99*4882a593Smuzhiyun 	.name		= "viper-pcmcia",
100*4882a593Smuzhiyun 	.id		= -1,
101*4882a593Smuzhiyun 	.dev		= {
102*4882a593Smuzhiyun 		.platform_data	= &viper_pcmcia_info,
103*4882a593Smuzhiyun 	},
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /*
107*4882a593Smuzhiyun  * The CPLD version register was not present on VIPER boards prior to
108*4882a593Smuzhiyun  * v2i1. On v1 boards where the version register is not present we
109*4882a593Smuzhiyun  * will just read back the previous value from the databus.
110*4882a593Smuzhiyun  *
111*4882a593Smuzhiyun  * Therefore we do two reads. The first time we write 0 to the
112*4882a593Smuzhiyun  * (read-only) register before reading and the second time we write
113*4882a593Smuzhiyun  * 0xff first. If the two reads do not match or they read back as 0xff
114*4882a593Smuzhiyun  * or 0x00 then we have version 1 hardware.
115*4882a593Smuzhiyun  */
viper_hw_version(void)116*4882a593Smuzhiyun static u8 viper_hw_version(void)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	u8 v1, v2;
119*4882a593Smuzhiyun 	unsigned long flags;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	local_irq_save(flags);
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	VIPER_VERSION = 0;
124*4882a593Smuzhiyun 	v1 = VIPER_VERSION;
125*4882a593Smuzhiyun 	VIPER_VERSION = 0xff;
126*4882a593Smuzhiyun 	v2 = VIPER_VERSION;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	v1 = (v1 != v2 || v1 == 0xff) ? 0 : v1;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	local_irq_restore(flags);
131*4882a593Smuzhiyun 	return v1;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /* CPU system core operations. */
viper_cpu_suspend(void)135*4882a593Smuzhiyun static int viper_cpu_suspend(void)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	viper_icr_set_bit(VIPER_ICR_R_DIS);
138*4882a593Smuzhiyun 	return 0;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
viper_cpu_resume(void)141*4882a593Smuzhiyun static void viper_cpu_resume(void)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	viper_icr_clear_bit(VIPER_ICR_R_DIS);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun static struct syscore_ops viper_cpu_syscore_ops = {
147*4882a593Smuzhiyun 	.suspend	= viper_cpu_suspend,
148*4882a593Smuzhiyun 	.resume		= viper_cpu_resume,
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun static unsigned int current_voltage_divisor;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun /*
154*4882a593Smuzhiyun  * If force is not true then step from existing to new divisor. If
155*4882a593Smuzhiyun  * force is true then jump straight to the new divisor. Stepping is
156*4882a593Smuzhiyun  * used because if the jump in voltage is too large, the VCC can dip
157*4882a593Smuzhiyun  * too low and the regulator cuts out.
158*4882a593Smuzhiyun  *
159*4882a593Smuzhiyun  * force can be used to initialize the divisor to a know state by
160*4882a593Smuzhiyun  * setting the value for the current clock speed, since we are already
161*4882a593Smuzhiyun  * running at that speed we know the voltage should be pretty close so
162*4882a593Smuzhiyun  * the jump won't be too large
163*4882a593Smuzhiyun  */
viper_set_core_cpu_voltage(unsigned long khz,int force)164*4882a593Smuzhiyun static void viper_set_core_cpu_voltage(unsigned long khz, int force)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	int i = 0;
167*4882a593Smuzhiyun 	unsigned int divisor = 0;
168*4882a593Smuzhiyun 	const char *v;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	if (khz < 200000) {
171*4882a593Smuzhiyun 		v = "1.0"; divisor = 0xfff;
172*4882a593Smuzhiyun 	} else if (khz < 300000) {
173*4882a593Smuzhiyun 		v = "1.1"; divisor = 0xde5;
174*4882a593Smuzhiyun 	} else {
175*4882a593Smuzhiyun 		v = "1.3"; divisor = 0x325;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	pr_debug("viper: setting CPU core voltage to %sV at %d.%03dMHz\n",
179*4882a593Smuzhiyun 		 v, (int)khz / 1000, (int)khz % 1000);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun #define STEP 0x100
182*4882a593Smuzhiyun 	do {
183*4882a593Smuzhiyun 		int step;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 		if (force)
186*4882a593Smuzhiyun 			step = divisor;
187*4882a593Smuzhiyun 		else if (current_voltage_divisor < divisor - STEP)
188*4882a593Smuzhiyun 			step = current_voltage_divisor + STEP;
189*4882a593Smuzhiyun 		else if (current_voltage_divisor > divisor + STEP)
190*4882a593Smuzhiyun 			step = current_voltage_divisor - STEP;
191*4882a593Smuzhiyun 		else
192*4882a593Smuzhiyun 			step = divisor;
193*4882a593Smuzhiyun 		force = 0;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 		gpio_set_value(VIPER_PSU_CLK_GPIO, 0);
196*4882a593Smuzhiyun 		gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 		for (i = 1 << 11 ; i > 0 ; i >>= 1) {
199*4882a593Smuzhiyun 			udelay(1);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 			gpio_set_value(VIPER_PSU_DATA_GPIO, step & i);
202*4882a593Smuzhiyun 			udelay(1);
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 			gpio_set_value(VIPER_PSU_CLK_GPIO, 1);
205*4882a593Smuzhiyun 			udelay(1);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 			gpio_set_value(VIPER_PSU_CLK_GPIO, 0);
208*4882a593Smuzhiyun 		}
209*4882a593Smuzhiyun 		udelay(1);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 		gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 1);
212*4882a593Smuzhiyun 		udelay(1);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 		gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 		current_voltage_divisor = step;
217*4882a593Smuzhiyun 	} while (current_voltage_divisor != divisor);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun /* Interrupt handling */
221*4882a593Smuzhiyun static unsigned long viper_irq_enabled_mask;
222*4882a593Smuzhiyun static const int viper_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, 9, 14, 15 };
223*4882a593Smuzhiyun static const int viper_isa_irq_map[] = {
224*4882a593Smuzhiyun 	0,		/* ISA irq #0, invalid */
225*4882a593Smuzhiyun 	0,		/* ISA irq #1, invalid */
226*4882a593Smuzhiyun 	0,		/* ISA irq #2, invalid */
227*4882a593Smuzhiyun 	1 << 0,		/* ISA irq #3 */
228*4882a593Smuzhiyun 	1 << 1,		/* ISA irq #4 */
229*4882a593Smuzhiyun 	1 << 2,		/* ISA irq #5 */
230*4882a593Smuzhiyun 	1 << 3,		/* ISA irq #6 */
231*4882a593Smuzhiyun 	1 << 4,		/* ISA irq #7 */
232*4882a593Smuzhiyun 	0,		/* ISA irq #8, invalid */
233*4882a593Smuzhiyun 	1 << 8,		/* ISA irq #9 */
234*4882a593Smuzhiyun 	1 << 5,		/* ISA irq #10 */
235*4882a593Smuzhiyun 	1 << 6,		/* ISA irq #11 */
236*4882a593Smuzhiyun 	1 << 7,		/* ISA irq #12 */
237*4882a593Smuzhiyun 	0,		/* ISA irq #13, invalid */
238*4882a593Smuzhiyun 	1 << 9,		/* ISA irq #14 */
239*4882a593Smuzhiyun 	1 << 10,	/* ISA irq #15 */
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun 
viper_irq_to_bitmask(unsigned int irq)242*4882a593Smuzhiyun static inline int viper_irq_to_bitmask(unsigned int irq)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun 	return viper_isa_irq_map[irq - PXA_ISA_IRQ(0)];
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun 
viper_bit_to_irq(int bit)247*4882a593Smuzhiyun static inline int viper_bit_to_irq(int bit)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	return viper_isa_irqs[bit] + PXA_ISA_IRQ(0);
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun 
viper_ack_irq(struct irq_data * d)252*4882a593Smuzhiyun static void viper_ack_irq(struct irq_data *d)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun 	int viper_irq = viper_irq_to_bitmask(d->irq);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	if (viper_irq & 0xff)
257*4882a593Smuzhiyun 		VIPER_LO_IRQ_STATUS = viper_irq;
258*4882a593Smuzhiyun 	else
259*4882a593Smuzhiyun 		VIPER_HI_IRQ_STATUS = (viper_irq >> 8);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
viper_mask_irq(struct irq_data * d)262*4882a593Smuzhiyun static void viper_mask_irq(struct irq_data *d)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun 	viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(d->irq));
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
viper_unmask_irq(struct irq_data * d)267*4882a593Smuzhiyun static void viper_unmask_irq(struct irq_data *d)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	viper_irq_enabled_mask |= viper_irq_to_bitmask(d->irq);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
viper_irq_pending(void)272*4882a593Smuzhiyun static inline unsigned long viper_irq_pending(void)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun 	return (VIPER_HI_IRQ_STATUS << 8 | VIPER_LO_IRQ_STATUS) &
275*4882a593Smuzhiyun 			viper_irq_enabled_mask;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun 
viper_irq_handler(struct irq_desc * desc)278*4882a593Smuzhiyun static void viper_irq_handler(struct irq_desc *desc)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun 	unsigned int irq;
281*4882a593Smuzhiyun 	unsigned long pending;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	pending = viper_irq_pending();
284*4882a593Smuzhiyun 	do {
285*4882a593Smuzhiyun 		/* we're in a chained irq handler,
286*4882a593Smuzhiyun 		 * so ack the interrupt by hand */
287*4882a593Smuzhiyun 		desc->irq_data.chip->irq_ack(&desc->irq_data);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 		if (likely(pending)) {
290*4882a593Smuzhiyun 			irq = viper_bit_to_irq(__ffs(pending));
291*4882a593Smuzhiyun 			generic_handle_irq(irq);
292*4882a593Smuzhiyun 		}
293*4882a593Smuzhiyun 		pending = viper_irq_pending();
294*4882a593Smuzhiyun 	} while (pending);
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun static struct irq_chip viper_irq_chip = {
298*4882a593Smuzhiyun 	.name		= "ISA",
299*4882a593Smuzhiyun 	.irq_ack	= viper_ack_irq,
300*4882a593Smuzhiyun 	.irq_mask	= viper_mask_irq,
301*4882a593Smuzhiyun 	.irq_unmask	= viper_unmask_irq
302*4882a593Smuzhiyun };
303*4882a593Smuzhiyun 
viper_init_irq(void)304*4882a593Smuzhiyun static void __init viper_init_irq(void)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun 	int level;
307*4882a593Smuzhiyun 	int isa_irq;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	pxa25x_init_irq();
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	/* setup ISA IRQs */
312*4882a593Smuzhiyun 	for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
313*4882a593Smuzhiyun 		isa_irq = viper_bit_to_irq(level);
314*4882a593Smuzhiyun 		irq_set_chip_and_handler(isa_irq, &viper_irq_chip,
315*4882a593Smuzhiyun 					 handle_edge_irq);
316*4882a593Smuzhiyun 		irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
317*4882a593Smuzhiyun 	}
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
320*4882a593Smuzhiyun 				viper_irq_handler);
321*4882a593Smuzhiyun 	irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun /* Flat Panel */
325*4882a593Smuzhiyun static struct pxafb_mode_info fb_mode_info[] = {
326*4882a593Smuzhiyun 	{
327*4882a593Smuzhiyun 		.pixclock	= 157500,
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 		.xres		= 320,
330*4882a593Smuzhiyun 		.yres		= 240,
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 		.bpp		= 16,
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 		.hsync_len	= 63,
335*4882a593Smuzhiyun 		.left_margin	= 7,
336*4882a593Smuzhiyun 		.right_margin	= 13,
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 		.vsync_len	= 20,
339*4882a593Smuzhiyun 		.upper_margin	= 0,
340*4882a593Smuzhiyun 		.lower_margin	= 0,
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 		.sync		= 0,
343*4882a593Smuzhiyun 	},
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun static struct pxafb_mach_info fb_info = {
347*4882a593Smuzhiyun 	.modes			= fb_mode_info,
348*4882a593Smuzhiyun 	.num_modes		= 1,
349*4882a593Smuzhiyun 	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
350*4882a593Smuzhiyun };
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun static struct pwm_lookup viper_pwm_lookup[] = {
353*4882a593Smuzhiyun 	PWM_LOOKUP("pxa25x-pwm.0", 0, "pwm-backlight.0", NULL, 1000000,
354*4882a593Smuzhiyun 		   PWM_POLARITY_NORMAL),
355*4882a593Smuzhiyun };
356*4882a593Smuzhiyun 
viper_backlight_init(struct device * dev)357*4882a593Smuzhiyun static int viper_backlight_init(struct device *dev)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun 	int ret;
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	/* GPIO9 and 10 control FB backlight. Initialise to off */
362*4882a593Smuzhiyun 	ret = gpio_request(VIPER_BCKLIGHT_EN_GPIO, "Backlight");
363*4882a593Smuzhiyun 	if (ret)
364*4882a593Smuzhiyun 		goto err_request_bckl;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	ret = gpio_request(VIPER_LCD_EN_GPIO, "LCD");
367*4882a593Smuzhiyun 	if (ret)
368*4882a593Smuzhiyun 		goto err_request_lcd;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	ret = gpio_direction_output(VIPER_BCKLIGHT_EN_GPIO, 0);
371*4882a593Smuzhiyun 	if (ret)
372*4882a593Smuzhiyun 		goto err_dir;
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	ret = gpio_direction_output(VIPER_LCD_EN_GPIO, 0);
375*4882a593Smuzhiyun 	if (ret)
376*4882a593Smuzhiyun 		goto err_dir;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	return 0;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun err_dir:
381*4882a593Smuzhiyun 	gpio_free(VIPER_LCD_EN_GPIO);
382*4882a593Smuzhiyun err_request_lcd:
383*4882a593Smuzhiyun 	gpio_free(VIPER_BCKLIGHT_EN_GPIO);
384*4882a593Smuzhiyun err_request_bckl:
385*4882a593Smuzhiyun 	dev_err(dev, "Failed to setup LCD GPIOs\n");
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	return ret;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
viper_backlight_notify(struct device * dev,int brightness)390*4882a593Smuzhiyun static int viper_backlight_notify(struct device *dev, int brightness)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun 	gpio_set_value(VIPER_LCD_EN_GPIO, !!brightness);
393*4882a593Smuzhiyun 	gpio_set_value(VIPER_BCKLIGHT_EN_GPIO, !!brightness);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	return brightness;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun 
viper_backlight_exit(struct device * dev)398*4882a593Smuzhiyun static void viper_backlight_exit(struct device *dev)
399*4882a593Smuzhiyun {
400*4882a593Smuzhiyun 	gpio_free(VIPER_LCD_EN_GPIO);
401*4882a593Smuzhiyun 	gpio_free(VIPER_BCKLIGHT_EN_GPIO);
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun static struct platform_pwm_backlight_data viper_backlight_data = {
405*4882a593Smuzhiyun 	.max_brightness	= 100,
406*4882a593Smuzhiyun 	.dft_brightness	= 100,
407*4882a593Smuzhiyun 	.init		= viper_backlight_init,
408*4882a593Smuzhiyun 	.notify		= viper_backlight_notify,
409*4882a593Smuzhiyun 	.exit		= viper_backlight_exit,
410*4882a593Smuzhiyun };
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun static struct platform_device viper_backlight_device = {
413*4882a593Smuzhiyun 	.name		= "pwm-backlight",
414*4882a593Smuzhiyun 	.dev		= {
415*4882a593Smuzhiyun 		.parent		= &pxa25x_device_pwm0.dev,
416*4882a593Smuzhiyun 		.platform_data	= &viper_backlight_data,
417*4882a593Smuzhiyun 	},
418*4882a593Smuzhiyun };
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun /* Ethernet */
421*4882a593Smuzhiyun static struct resource smc91x_resources[] = {
422*4882a593Smuzhiyun 	[0] = {
423*4882a593Smuzhiyun 		.name	= "smc91x-regs",
424*4882a593Smuzhiyun 		.start  = VIPER_ETH_PHYS + 0x300,
425*4882a593Smuzhiyun 		.end    = VIPER_ETH_PHYS + 0x30f,
426*4882a593Smuzhiyun 		.flags  = IORESOURCE_MEM,
427*4882a593Smuzhiyun 	},
428*4882a593Smuzhiyun 	[1] = {
429*4882a593Smuzhiyun 		.start  = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO),
430*4882a593Smuzhiyun 		.end    = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO),
431*4882a593Smuzhiyun 		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
432*4882a593Smuzhiyun 	},
433*4882a593Smuzhiyun 	[2] = {
434*4882a593Smuzhiyun 		.name	= "smc91x-data32",
435*4882a593Smuzhiyun 		.start  = VIPER_ETH_DATA_PHYS,
436*4882a593Smuzhiyun 		.end    = VIPER_ETH_DATA_PHYS + 3,
437*4882a593Smuzhiyun 		.flags  = IORESOURCE_MEM,
438*4882a593Smuzhiyun 	},
439*4882a593Smuzhiyun };
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun static struct smc91x_platdata viper_smc91x_info = {
442*4882a593Smuzhiyun 	.flags	= SMC91X_USE_16BIT | SMC91X_NOWAIT,
443*4882a593Smuzhiyun 	.leda	= RPC_LED_100_10,
444*4882a593Smuzhiyun 	.ledb	= RPC_LED_TX_RX,
445*4882a593Smuzhiyun };
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun static struct platform_device smc91x_device = {
448*4882a593Smuzhiyun 	.name		= "smc91x",
449*4882a593Smuzhiyun 	.id		= -1,
450*4882a593Smuzhiyun 	.num_resources  = ARRAY_SIZE(smc91x_resources),
451*4882a593Smuzhiyun 	.resource       = smc91x_resources,
452*4882a593Smuzhiyun 	.dev		= {
453*4882a593Smuzhiyun 		.platform_data	= &viper_smc91x_info,
454*4882a593Smuzhiyun 	},
455*4882a593Smuzhiyun };
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun /* i2c */
458*4882a593Smuzhiyun static struct gpiod_lookup_table viper_i2c_gpiod_table = {
459*4882a593Smuzhiyun 	.dev_id		= "i2c-gpio.1",
460*4882a593Smuzhiyun 	.table		= {
461*4882a593Smuzhiyun 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SDA_GPIO,
462*4882a593Smuzhiyun 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
463*4882a593Smuzhiyun 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SCL_GPIO,
464*4882a593Smuzhiyun 				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
465*4882a593Smuzhiyun 	},
466*4882a593Smuzhiyun };
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun static struct i2c_gpio_platform_data i2c_bus_data = {
469*4882a593Smuzhiyun 	.udelay  = 10,
470*4882a593Smuzhiyun 	.timeout = HZ,
471*4882a593Smuzhiyun };
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun static struct platform_device i2c_bus_device = {
474*4882a593Smuzhiyun 	.name		= "i2c-gpio",
475*4882a593Smuzhiyun 	.id		= 1, /* pxa2xx-i2c is bus 0, so start at 1 */
476*4882a593Smuzhiyun 	.dev = {
477*4882a593Smuzhiyun 		.platform_data = &i2c_bus_data,
478*4882a593Smuzhiyun 	}
479*4882a593Smuzhiyun };
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun static struct i2c_board_info __initdata viper_i2c_devices[] = {
482*4882a593Smuzhiyun 	{
483*4882a593Smuzhiyun 		I2C_BOARD_INFO("ds1338", 0x68),
484*4882a593Smuzhiyun 	},
485*4882a593Smuzhiyun };
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun /*
488*4882a593Smuzhiyun  * Serial configuration:
489*4882a593Smuzhiyun  * You can either have the standard PXA ports driven by the PXA driver,
490*4882a593Smuzhiyun  * or all the ports (PXA + 16850) driven by the 8250 driver.
491*4882a593Smuzhiyun  * Choose your poison.
492*4882a593Smuzhiyun  */
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun static struct resource viper_serial_resources[] = {
495*4882a593Smuzhiyun #ifndef CONFIG_SERIAL_PXA
496*4882a593Smuzhiyun 	{
497*4882a593Smuzhiyun 		.start	= 0x40100000,
498*4882a593Smuzhiyun 		.end	= 0x4010001f,
499*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
500*4882a593Smuzhiyun 	},
501*4882a593Smuzhiyun 	{
502*4882a593Smuzhiyun 		.start	= 0x40200000,
503*4882a593Smuzhiyun 		.end	= 0x4020001f,
504*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
505*4882a593Smuzhiyun 	},
506*4882a593Smuzhiyun 	{
507*4882a593Smuzhiyun 		.start	= 0x40700000,
508*4882a593Smuzhiyun 		.end	= 0x4070001f,
509*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
510*4882a593Smuzhiyun 	},
511*4882a593Smuzhiyun 	{
512*4882a593Smuzhiyun 		.start	= VIPER_UARTA_PHYS,
513*4882a593Smuzhiyun 		.end	= VIPER_UARTA_PHYS + 0xf,
514*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
515*4882a593Smuzhiyun 	},
516*4882a593Smuzhiyun 	{
517*4882a593Smuzhiyun 		.start	= VIPER_UARTB_PHYS,
518*4882a593Smuzhiyun 		.end	= VIPER_UARTB_PHYS + 0xf,
519*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
520*4882a593Smuzhiyun 	},
521*4882a593Smuzhiyun #else
522*4882a593Smuzhiyun 	{
523*4882a593Smuzhiyun 		0,
524*4882a593Smuzhiyun 	},
525*4882a593Smuzhiyun #endif
526*4882a593Smuzhiyun };
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun static struct plat_serial8250_port serial_platform_data[] = {
529*4882a593Smuzhiyun #ifndef CONFIG_SERIAL_PXA
530*4882a593Smuzhiyun 	/* Internal UARTs */
531*4882a593Smuzhiyun 	{
532*4882a593Smuzhiyun 		.membase	= (void *)&FFUART,
533*4882a593Smuzhiyun 		.mapbase	= __PREG(FFUART),
534*4882a593Smuzhiyun 		.irq		= IRQ_FFUART,
535*4882a593Smuzhiyun 		.uartclk	= 921600 * 16,
536*4882a593Smuzhiyun 		.regshift	= 2,
537*4882a593Smuzhiyun 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
538*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
539*4882a593Smuzhiyun 	},
540*4882a593Smuzhiyun 	{
541*4882a593Smuzhiyun 		.membase	= (void *)&BTUART,
542*4882a593Smuzhiyun 		.mapbase	= __PREG(BTUART),
543*4882a593Smuzhiyun 		.irq		= IRQ_BTUART,
544*4882a593Smuzhiyun 		.uartclk	= 921600 * 16,
545*4882a593Smuzhiyun 		.regshift	= 2,
546*4882a593Smuzhiyun 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
547*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
548*4882a593Smuzhiyun 	},
549*4882a593Smuzhiyun 	{
550*4882a593Smuzhiyun 		.membase	= (void *)&STUART,
551*4882a593Smuzhiyun 		.mapbase	= __PREG(STUART),
552*4882a593Smuzhiyun 		.irq		= IRQ_STUART,
553*4882a593Smuzhiyun 		.uartclk	= 921600 * 16,
554*4882a593Smuzhiyun 		.regshift	= 2,
555*4882a593Smuzhiyun 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
556*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
557*4882a593Smuzhiyun 	},
558*4882a593Smuzhiyun 	/* External UARTs */
559*4882a593Smuzhiyun 	{
560*4882a593Smuzhiyun 		.mapbase	= VIPER_UARTA_PHYS,
561*4882a593Smuzhiyun 		.irq		= PXA_GPIO_TO_IRQ(VIPER_UARTA_GPIO),
562*4882a593Smuzhiyun 		.irqflags	= IRQF_TRIGGER_RISING,
563*4882a593Smuzhiyun 		.uartclk	= 1843200,
564*4882a593Smuzhiyun 		.regshift	= 1,
565*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
566*4882a593Smuzhiyun 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP |
567*4882a593Smuzhiyun 				  UPF_SKIP_TEST,
568*4882a593Smuzhiyun 	},
569*4882a593Smuzhiyun 	{
570*4882a593Smuzhiyun 		.mapbase	= VIPER_UARTB_PHYS,
571*4882a593Smuzhiyun 		.irq		= PXA_GPIO_TO_IRQ(VIPER_UARTB_GPIO),
572*4882a593Smuzhiyun 		.irqflags	= IRQF_TRIGGER_RISING,
573*4882a593Smuzhiyun 		.uartclk	= 1843200,
574*4882a593Smuzhiyun 		.regshift	= 1,
575*4882a593Smuzhiyun 		.iotype		= UPIO_MEM,
576*4882a593Smuzhiyun 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP |
577*4882a593Smuzhiyun 				  UPF_SKIP_TEST,
578*4882a593Smuzhiyun 	},
579*4882a593Smuzhiyun #endif
580*4882a593Smuzhiyun 	{ },
581*4882a593Smuzhiyun };
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun static struct platform_device serial_device = {
584*4882a593Smuzhiyun 	.name			= "serial8250",
585*4882a593Smuzhiyun 	.id			= 0,
586*4882a593Smuzhiyun 	.dev			= {
587*4882a593Smuzhiyun 		.platform_data	= serial_platform_data,
588*4882a593Smuzhiyun 	},
589*4882a593Smuzhiyun 	.num_resources		= ARRAY_SIZE(viper_serial_resources),
590*4882a593Smuzhiyun 	.resource		= viper_serial_resources,
591*4882a593Smuzhiyun };
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun /* USB */
isp116x_delay(struct device * dev,int delay)594*4882a593Smuzhiyun static void isp116x_delay(struct device *dev, int delay)
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun 	ndelay(delay);
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun static struct resource isp116x_resources[] = {
600*4882a593Smuzhiyun 	[0] = { /* DATA */
601*4882a593Smuzhiyun 		.start  = VIPER_USB_PHYS + 0,
602*4882a593Smuzhiyun 		.end    = VIPER_USB_PHYS + 1,
603*4882a593Smuzhiyun 		.flags  = IORESOURCE_MEM,
604*4882a593Smuzhiyun 	},
605*4882a593Smuzhiyun 	[1] = { /* ADDR */
606*4882a593Smuzhiyun 		.start  = VIPER_USB_PHYS + 2,
607*4882a593Smuzhiyun 		.end    = VIPER_USB_PHYS + 3,
608*4882a593Smuzhiyun 		.flags  = IORESOURCE_MEM,
609*4882a593Smuzhiyun 	},
610*4882a593Smuzhiyun 	[2] = {
611*4882a593Smuzhiyun 		.start  = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO),
612*4882a593Smuzhiyun 		.end    = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO),
613*4882a593Smuzhiyun 		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
614*4882a593Smuzhiyun 	},
615*4882a593Smuzhiyun };
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun /* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */
618*4882a593Smuzhiyun static struct isp116x_platform_data isp116x_platform_data = {
619*4882a593Smuzhiyun 	/* Enable internal resistors on downstream ports */
620*4882a593Smuzhiyun 	.sel15Kres		= 1,
621*4882a593Smuzhiyun 	/* On-chip overcurrent protection */
622*4882a593Smuzhiyun 	.oc_enable		= 1,
623*4882a593Smuzhiyun 	/* INT output polarity */
624*4882a593Smuzhiyun 	.int_act_high		= 1,
625*4882a593Smuzhiyun 	/* INT edge or level triggered */
626*4882a593Smuzhiyun 	.int_edge_triggered	= 0,
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	/* WAKEUP pin connected - NOT SUPPORTED  */
629*4882a593Smuzhiyun 	/* .remote_wakeup_connected = 0, */
630*4882a593Smuzhiyun 	/* Wakeup by devices on usb bus enabled */
631*4882a593Smuzhiyun 	.remote_wakeup_enable	= 0,
632*4882a593Smuzhiyun 	.delay			= isp116x_delay,
633*4882a593Smuzhiyun };
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun static struct platform_device isp116x_device = {
636*4882a593Smuzhiyun 	.name			= "isp116x-hcd",
637*4882a593Smuzhiyun 	.id			= -1,
638*4882a593Smuzhiyun 	.num_resources  	= ARRAY_SIZE(isp116x_resources),
639*4882a593Smuzhiyun 	.resource       	= isp116x_resources,
640*4882a593Smuzhiyun 	.dev			= {
641*4882a593Smuzhiyun 		.platform_data	= &isp116x_platform_data,
642*4882a593Smuzhiyun 	},
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun };
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun /* MTD */
647*4882a593Smuzhiyun static struct resource mtd_resources[] = {
648*4882a593Smuzhiyun 	[0] = {	/* RedBoot config + filesystem flash */
649*4882a593Smuzhiyun 		.start	= VIPER_FLASH_PHYS,
650*4882a593Smuzhiyun 		.end	= VIPER_FLASH_PHYS + SZ_32M - 1,
651*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
652*4882a593Smuzhiyun 	},
653*4882a593Smuzhiyun 	[1] = {	/* Boot flash */
654*4882a593Smuzhiyun 		.start	= VIPER_BOOT_PHYS,
655*4882a593Smuzhiyun 		.end	= VIPER_BOOT_PHYS + SZ_1M - 1,
656*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
657*4882a593Smuzhiyun 	},
658*4882a593Smuzhiyun 	[2] = { /*
659*4882a593Smuzhiyun 		 * SRAM size is actually 256KB, 8bits, with a sparse mapping
660*4882a593Smuzhiyun 		 * (each byte is on a 16bit boundary).
661*4882a593Smuzhiyun 		 */
662*4882a593Smuzhiyun 		.start	= _VIPER_SRAM_BASE,
663*4882a593Smuzhiyun 		.end	= _VIPER_SRAM_BASE + SZ_512K - 1,
664*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
665*4882a593Smuzhiyun 	},
666*4882a593Smuzhiyun };
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun static struct mtd_partition viper_boot_flash_partition = {
669*4882a593Smuzhiyun 	.name		= "RedBoot",
670*4882a593Smuzhiyun 	.size		= SZ_1M,
671*4882a593Smuzhiyun 	.offset		= 0,
672*4882a593Smuzhiyun 	.mask_flags	= MTD_WRITEABLE,	/* force R/O */
673*4882a593Smuzhiyun };
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun static struct physmap_flash_data viper_flash_data[] = {
676*4882a593Smuzhiyun 	[0] = {
677*4882a593Smuzhiyun 		.width		= 2,
678*4882a593Smuzhiyun 		.parts		= NULL,
679*4882a593Smuzhiyun 		.nr_parts	= 0,
680*4882a593Smuzhiyun 	},
681*4882a593Smuzhiyun 	[1] = {
682*4882a593Smuzhiyun 		.width		= 2,
683*4882a593Smuzhiyun 		.parts		= &viper_boot_flash_partition,
684*4882a593Smuzhiyun 		.nr_parts	= 1,
685*4882a593Smuzhiyun 	},
686*4882a593Smuzhiyun };
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun static struct platform_device viper_mtd_devices[] = {
689*4882a593Smuzhiyun 	[0] = {
690*4882a593Smuzhiyun 		.name		= "physmap-flash",
691*4882a593Smuzhiyun 		.id		= 0,
692*4882a593Smuzhiyun 		.dev		= {
693*4882a593Smuzhiyun 			.platform_data	= &viper_flash_data[0],
694*4882a593Smuzhiyun 		},
695*4882a593Smuzhiyun 		.resource	= &mtd_resources[0],
696*4882a593Smuzhiyun 		.num_resources	= 1,
697*4882a593Smuzhiyun 	},
698*4882a593Smuzhiyun 	[1] = {
699*4882a593Smuzhiyun 		.name		= "physmap-flash",
700*4882a593Smuzhiyun 		.id		= 1,
701*4882a593Smuzhiyun 		.dev		= {
702*4882a593Smuzhiyun 			.platform_data	= &viper_flash_data[1],
703*4882a593Smuzhiyun 		},
704*4882a593Smuzhiyun 		.resource	= &mtd_resources[1],
705*4882a593Smuzhiyun 		.num_resources	= 1,
706*4882a593Smuzhiyun 	},
707*4882a593Smuzhiyun };
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun static struct platform_device *viper_devs[] __initdata = {
710*4882a593Smuzhiyun 	&smc91x_device,
711*4882a593Smuzhiyun 	&i2c_bus_device,
712*4882a593Smuzhiyun 	&serial_device,
713*4882a593Smuzhiyun 	&isp116x_device,
714*4882a593Smuzhiyun 	&viper_mtd_devices[0],
715*4882a593Smuzhiyun 	&viper_mtd_devices[1],
716*4882a593Smuzhiyun 	&viper_backlight_device,
717*4882a593Smuzhiyun 	&viper_pcmcia_device,
718*4882a593Smuzhiyun };
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun static mfp_cfg_t viper_pin_config[] __initdata = {
721*4882a593Smuzhiyun 	/* Chip selects */
722*4882a593Smuzhiyun 	GPIO15_nCS_1,
723*4882a593Smuzhiyun 	GPIO78_nCS_2,
724*4882a593Smuzhiyun 	GPIO79_nCS_3,
725*4882a593Smuzhiyun 	GPIO80_nCS_4,
726*4882a593Smuzhiyun 	GPIO33_nCS_5,
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	/* AC97 */
729*4882a593Smuzhiyun 	GPIO28_AC97_BITCLK,
730*4882a593Smuzhiyun 	GPIO29_AC97_SDATA_IN_0,
731*4882a593Smuzhiyun 	GPIO30_AC97_SDATA_OUT,
732*4882a593Smuzhiyun 	GPIO31_AC97_SYNC,
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun 	/* FP Backlight */
735*4882a593Smuzhiyun 	GPIO9_GPIO, 				/* VIPER_BCKLIGHT_EN_GPIO */
736*4882a593Smuzhiyun 	GPIO10_GPIO,				/* VIPER_LCD_EN_GPIO */
737*4882a593Smuzhiyun 	GPIO16_PWM0_OUT,
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun 	/* Ethernet PHY Ready */
740*4882a593Smuzhiyun 	GPIO18_RDY,
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun 	/* Serial shutdown */
743*4882a593Smuzhiyun 	GPIO12_GPIO | MFP_LPM_DRIVE_HIGH,	/* VIPER_UART_SHDN_GPIO */
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun 	/* Compact-Flash / PC104 */
746*4882a593Smuzhiyun 	GPIO48_nPOE,
747*4882a593Smuzhiyun 	GPIO49_nPWE,
748*4882a593Smuzhiyun 	GPIO50_nPIOR,
749*4882a593Smuzhiyun 	GPIO51_nPIOW,
750*4882a593Smuzhiyun 	GPIO52_nPCE_1,
751*4882a593Smuzhiyun 	GPIO53_nPCE_2,
752*4882a593Smuzhiyun 	GPIO54_nPSKTSEL,
753*4882a593Smuzhiyun 	GPIO55_nPREG,
754*4882a593Smuzhiyun 	GPIO56_nPWAIT,
755*4882a593Smuzhiyun 	GPIO57_nIOIS16,
756*4882a593Smuzhiyun 	GPIO8_GPIO,				/* VIPER_CF_RDY_GPIO */
757*4882a593Smuzhiyun 	GPIO32_GPIO,				/* VIPER_CF_CD_GPIO */
758*4882a593Smuzhiyun 	GPIO82_GPIO,				/* VIPER_CF_POWER_GPIO */
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	/* Integrated UPS control */
761*4882a593Smuzhiyun 	GPIO20_GPIO,				/* VIPER_UPS_GPIO */
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun 	/* Vcc regulator control */
764*4882a593Smuzhiyun 	GPIO6_GPIO,				/* VIPER_PSU_DATA_GPIO */
765*4882a593Smuzhiyun 	GPIO11_GPIO,				/* VIPER_PSU_CLK_GPIO */
766*4882a593Smuzhiyun 	GPIO19_GPIO,				/* VIPER_PSU_nCS_LD_GPIO */
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 	/* i2c busses */
769*4882a593Smuzhiyun 	GPIO26_GPIO,				/* VIPER_TPM_I2C_SDA_GPIO */
770*4882a593Smuzhiyun 	GPIO27_GPIO,				/* VIPER_TPM_I2C_SCL_GPIO */
771*4882a593Smuzhiyun 	GPIO83_GPIO,				/* VIPER_RTC_I2C_SDA_GPIO */
772*4882a593Smuzhiyun 	GPIO84_GPIO,				/* VIPER_RTC_I2C_SCL_GPIO */
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 	/* PC/104 Interrupt */
775*4882a593Smuzhiyun 	GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,	/* VIPER_CPLD_GPIO */
776*4882a593Smuzhiyun };
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun static unsigned long viper_tpm;
779*4882a593Smuzhiyun 
viper_tpm_setup(char * str)780*4882a593Smuzhiyun static int __init viper_tpm_setup(char *str)
781*4882a593Smuzhiyun {
782*4882a593Smuzhiyun 	return kstrtoul(str, 10, &viper_tpm) >= 0;
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun __setup("tpm=", viper_tpm_setup);
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun struct gpiod_lookup_table viper_tpm_i2c_gpiod_table = {
788*4882a593Smuzhiyun 	.dev_id = "i2c-gpio.2",
789*4882a593Smuzhiyun 	.table = {
790*4882a593Smuzhiyun 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SDA_GPIO,
791*4882a593Smuzhiyun 				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
792*4882a593Smuzhiyun 		GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SCL_GPIO,
793*4882a593Smuzhiyun 				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
794*4882a593Smuzhiyun 	},
795*4882a593Smuzhiyun };
796*4882a593Smuzhiyun 
viper_tpm_init(void)797*4882a593Smuzhiyun static void __init viper_tpm_init(void)
798*4882a593Smuzhiyun {
799*4882a593Smuzhiyun 	struct platform_device *tpm_device;
800*4882a593Smuzhiyun 	struct i2c_gpio_platform_data i2c_tpm_data = {
801*4882a593Smuzhiyun 		.udelay  = 10,
802*4882a593Smuzhiyun 		.timeout = HZ,
803*4882a593Smuzhiyun 	};
804*4882a593Smuzhiyun 	char *errstr;
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun 	/* Allocate TPM i2c bus if requested */
807*4882a593Smuzhiyun 	if (!viper_tpm)
808*4882a593Smuzhiyun 		return;
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	gpiod_add_lookup_table(&viper_tpm_i2c_gpiod_table);
811*4882a593Smuzhiyun 	tpm_device = platform_device_alloc("i2c-gpio", 2);
812*4882a593Smuzhiyun 	if (tpm_device) {
813*4882a593Smuzhiyun 		if (!platform_device_add_data(tpm_device,
814*4882a593Smuzhiyun 					      &i2c_tpm_data,
815*4882a593Smuzhiyun 					      sizeof(i2c_tpm_data))) {
816*4882a593Smuzhiyun 			if (platform_device_add(tpm_device)) {
817*4882a593Smuzhiyun 				errstr = "register TPM i2c bus";
818*4882a593Smuzhiyun 				goto error_free_tpm;
819*4882a593Smuzhiyun 			}
820*4882a593Smuzhiyun 		} else {
821*4882a593Smuzhiyun 			errstr = "allocate TPM i2c bus data";
822*4882a593Smuzhiyun 			goto error_free_tpm;
823*4882a593Smuzhiyun 		}
824*4882a593Smuzhiyun 	} else {
825*4882a593Smuzhiyun 		errstr = "allocate TPM i2c device";
826*4882a593Smuzhiyun 		goto error_tpm;
827*4882a593Smuzhiyun 	}
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun 	return;
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun error_free_tpm:
832*4882a593Smuzhiyun 	kfree(tpm_device);
833*4882a593Smuzhiyun error_tpm:
834*4882a593Smuzhiyun 	pr_err("viper: Couldn't %s, giving up\n", errstr);
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun 
viper_init_vcore_gpios(void)837*4882a593Smuzhiyun static void __init viper_init_vcore_gpios(void)
838*4882a593Smuzhiyun {
839*4882a593Smuzhiyun 	if (gpio_request(VIPER_PSU_DATA_GPIO, "PSU data"))
840*4882a593Smuzhiyun 		goto err_request_data;
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 	if (gpio_request(VIPER_PSU_CLK_GPIO, "PSU clock"))
843*4882a593Smuzhiyun 		goto err_request_clk;
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 	if (gpio_request(VIPER_PSU_nCS_LD_GPIO, "PSU cs"))
846*4882a593Smuzhiyun 		goto err_request_cs;
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun 	if (gpio_direction_output(VIPER_PSU_DATA_GPIO, 0) ||
849*4882a593Smuzhiyun 	    gpio_direction_output(VIPER_PSU_CLK_GPIO, 0) ||
850*4882a593Smuzhiyun 	    gpio_direction_output(VIPER_PSU_nCS_LD_GPIO, 0))
851*4882a593Smuzhiyun 		goto err_dir;
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun 	/* c/should assume redboot set the correct level ??? */
854*4882a593Smuzhiyun 	viper_set_core_cpu_voltage(get_clk_frequency_khz(0), 1);
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun 	return;
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun err_dir:
859*4882a593Smuzhiyun 	gpio_free(VIPER_PSU_nCS_LD_GPIO);
860*4882a593Smuzhiyun err_request_cs:
861*4882a593Smuzhiyun 	gpio_free(VIPER_PSU_CLK_GPIO);
862*4882a593Smuzhiyun err_request_clk:
863*4882a593Smuzhiyun 	gpio_free(VIPER_PSU_DATA_GPIO);
864*4882a593Smuzhiyun err_request_data:
865*4882a593Smuzhiyun 	pr_err("viper: Failed to setup vcore control GPIOs\n");
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun 
viper_init_serial_gpio(void)868*4882a593Smuzhiyun static void __init viper_init_serial_gpio(void)
869*4882a593Smuzhiyun {
870*4882a593Smuzhiyun 	if (gpio_request(VIPER_UART_SHDN_GPIO, "UARTs shutdown"))
871*4882a593Smuzhiyun 		goto err_request;
872*4882a593Smuzhiyun 
873*4882a593Smuzhiyun 	if (gpio_direction_output(VIPER_UART_SHDN_GPIO, 0))
874*4882a593Smuzhiyun 		goto err_dir;
875*4882a593Smuzhiyun 
876*4882a593Smuzhiyun 	return;
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun err_dir:
879*4882a593Smuzhiyun 	gpio_free(VIPER_UART_SHDN_GPIO);
880*4882a593Smuzhiyun err_request:
881*4882a593Smuzhiyun 	pr_err("viper: Failed to setup UART shutdown GPIO\n");
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun #ifdef CONFIG_CPU_FREQ
viper_cpufreq_notifier(struct notifier_block * nb,unsigned long val,void * data)885*4882a593Smuzhiyun static int viper_cpufreq_notifier(struct notifier_block *nb,
886*4882a593Smuzhiyun 				  unsigned long val, void *data)
887*4882a593Smuzhiyun {
888*4882a593Smuzhiyun 	struct cpufreq_freqs *freq = data;
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun 	/* TODO: Adjust timings??? */
891*4882a593Smuzhiyun 
892*4882a593Smuzhiyun 	switch (val) {
893*4882a593Smuzhiyun 	case CPUFREQ_PRECHANGE:
894*4882a593Smuzhiyun 		if (freq->old < freq->new) {
895*4882a593Smuzhiyun 			/* we are getting faster so raise the voltage
896*4882a593Smuzhiyun 			 * before we change freq */
897*4882a593Smuzhiyun 			viper_set_core_cpu_voltage(freq->new, 0);
898*4882a593Smuzhiyun 		}
899*4882a593Smuzhiyun 		break;
900*4882a593Smuzhiyun 	case CPUFREQ_POSTCHANGE:
901*4882a593Smuzhiyun 		if (freq->old > freq->new) {
902*4882a593Smuzhiyun 			/* we are slowing down so drop the power
903*4882a593Smuzhiyun 			 * after we change freq */
904*4882a593Smuzhiyun 			viper_set_core_cpu_voltage(freq->new, 0);
905*4882a593Smuzhiyun 		}
906*4882a593Smuzhiyun 		break;
907*4882a593Smuzhiyun 	default:
908*4882a593Smuzhiyun 		/* ignore */
909*4882a593Smuzhiyun 		break;
910*4882a593Smuzhiyun 	}
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	return 0;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun 
915*4882a593Smuzhiyun static struct notifier_block viper_cpufreq_notifier_block = {
916*4882a593Smuzhiyun 	.notifier_call  = viper_cpufreq_notifier
917*4882a593Smuzhiyun };
918*4882a593Smuzhiyun 
viper_init_cpufreq(void)919*4882a593Smuzhiyun static void __init viper_init_cpufreq(void)
920*4882a593Smuzhiyun {
921*4882a593Smuzhiyun 	if (cpufreq_register_notifier(&viper_cpufreq_notifier_block,
922*4882a593Smuzhiyun 				      CPUFREQ_TRANSITION_NOTIFIER))
923*4882a593Smuzhiyun 		pr_err("viper: Failed to setup cpufreq notifier\n");
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun #else
viper_init_cpufreq(void)926*4882a593Smuzhiyun static inline void viper_init_cpufreq(void) {}
927*4882a593Smuzhiyun #endif
928*4882a593Smuzhiyun 
viper_power_off(void)929*4882a593Smuzhiyun static void viper_power_off(void)
930*4882a593Smuzhiyun {
931*4882a593Smuzhiyun 	pr_notice("Shutting off UPS\n");
932*4882a593Smuzhiyun 	gpio_set_value(VIPER_UPS_GPIO, 1);
933*4882a593Smuzhiyun 	/* Spin to death... */
934*4882a593Smuzhiyun 	while (1);
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun 
viper_init(void)937*4882a593Smuzhiyun static void __init viper_init(void)
938*4882a593Smuzhiyun {
939*4882a593Smuzhiyun 	u8 version;
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	pm_power_off = viper_power_off;
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config));
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun 	pxa_set_ffuart_info(NULL);
946*4882a593Smuzhiyun 	pxa_set_btuart_info(NULL);
947*4882a593Smuzhiyun 	pxa_set_stuart_info(NULL);
948*4882a593Smuzhiyun 
949*4882a593Smuzhiyun 	/* Wake-up serial console */
950*4882a593Smuzhiyun 	viper_init_serial_gpio();
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	pxa_set_fb_info(NULL, &fb_info);
953*4882a593Smuzhiyun 
954*4882a593Smuzhiyun 	/* v1 hardware cannot use the datacs line */
955*4882a593Smuzhiyun 	version = viper_hw_version();
956*4882a593Smuzhiyun 	if (version == 0)
957*4882a593Smuzhiyun 		smc91x_device.num_resources--;
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	pxa_set_i2c_info(NULL);
960*4882a593Smuzhiyun 	gpiod_add_lookup_table(&viper_i2c_gpiod_table);
961*4882a593Smuzhiyun 	pwm_add_table(viper_pwm_lookup, ARRAY_SIZE(viper_pwm_lookup));
962*4882a593Smuzhiyun 	platform_add_devices(viper_devs, ARRAY_SIZE(viper_devs));
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	viper_init_vcore_gpios();
965*4882a593Smuzhiyun 	viper_init_cpufreq();
966*4882a593Smuzhiyun 
967*4882a593Smuzhiyun 	register_syscore_ops(&viper_cpu_syscore_ops);
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun 	if (version) {
970*4882a593Smuzhiyun 		pr_info("viper: hardware v%di%d detected. "
971*4882a593Smuzhiyun 			"CPLD revision %d.\n",
972*4882a593Smuzhiyun 			VIPER_BOARD_VERSION(version),
973*4882a593Smuzhiyun 			VIPER_BOARD_ISSUE(version),
974*4882a593Smuzhiyun 			VIPER_CPLD_REVISION(version));
975*4882a593Smuzhiyun 		system_rev = (VIPER_BOARD_VERSION(version) << 8) |
976*4882a593Smuzhiyun 			     (VIPER_BOARD_ISSUE(version) << 4) |
977*4882a593Smuzhiyun 			     VIPER_CPLD_REVISION(version);
978*4882a593Smuzhiyun 	} else {
979*4882a593Smuzhiyun 		pr_info("viper: No version register.\n");
980*4882a593Smuzhiyun 	}
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun 	i2c_register_board_info(1, ARRAY_AND_SIZE(viper_i2c_devices));
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun 	viper_tpm_init();
985*4882a593Smuzhiyun 	pxa_set_ac97_info(NULL);
986*4882a593Smuzhiyun }
987*4882a593Smuzhiyun 
988*4882a593Smuzhiyun static struct map_desc viper_io_desc[] __initdata = {
989*4882a593Smuzhiyun 	{
990*4882a593Smuzhiyun 		.virtual = VIPER_CPLD_BASE,
991*4882a593Smuzhiyun 		.pfn     = __phys_to_pfn(VIPER_CPLD_PHYS),
992*4882a593Smuzhiyun 		.length  = 0x00300000,
993*4882a593Smuzhiyun 		.type    = MT_DEVICE,
994*4882a593Smuzhiyun 	},
995*4882a593Smuzhiyun 	{
996*4882a593Smuzhiyun 		.virtual = VIPER_PC104IO_BASE,
997*4882a593Smuzhiyun 		.pfn     = __phys_to_pfn(0x30000000),
998*4882a593Smuzhiyun 		.length  = 0x00800000,
999*4882a593Smuzhiyun 		.type    = MT_DEVICE,
1000*4882a593Smuzhiyun 	},
1001*4882a593Smuzhiyun };
1002*4882a593Smuzhiyun 
viper_map_io(void)1003*4882a593Smuzhiyun static void __init viper_map_io(void)
1004*4882a593Smuzhiyun {
1005*4882a593Smuzhiyun 	pxa25x_map_io();
1006*4882a593Smuzhiyun 
1007*4882a593Smuzhiyun 	iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc));
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 	PCFR |= PCFR_OPDE;
1010*4882a593Smuzhiyun }
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
1013*4882a593Smuzhiyun 	/* Maintainer: Marc Zyngier <maz@misterjones.org> */
1014*4882a593Smuzhiyun 	.atag_offset	= 0x100,
1015*4882a593Smuzhiyun 	.map_io		= viper_map_io,
1016*4882a593Smuzhiyun 	.nr_irqs	= PXA_NR_IRQS,
1017*4882a593Smuzhiyun 	.init_irq	= viper_init_irq,
1018*4882a593Smuzhiyun 	.handle_irq	= pxa25x_handle_irq,
1019*4882a593Smuzhiyun 	.init_time	= pxa_timer_init,
1020*4882a593Smuzhiyun 	.init_machine	= viper_init,
1021*4882a593Smuzhiyun 	.restart	= pxa_restart,
1022*4882a593Smuzhiyun MACHINE_END
1023