xref: /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/stargate2.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  linux/arch/arm/mach-pxa/stargate2.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Author:	Ed C. Epp
6*4882a593Smuzhiyun  *  Created:	Nov 05, 2002
7*4882a593Smuzhiyun  *  Copyright:	Intel Corp.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  *  Modified 2009:  Jonathan Cameron <jic23@cam.ac.uk>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/sched.h>
16*4882a593Smuzhiyun #include <linux/bitops.h>
17*4882a593Smuzhiyun #include <linux/fb.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/regulator/machine.h>
21*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
22*4882a593Smuzhiyun #include <linux/mtd/plat-ram.h>
23*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <linux/platform_data/i2c-pxa.h>
26*4882a593Smuzhiyun #include <linux/platform_data/pcf857x.h>
27*4882a593Smuzhiyun #include <linux/smc91x.h>
28*4882a593Smuzhiyun #include <linux/gpio/machine.h>
29*4882a593Smuzhiyun #include <linux/gpio.h>
30*4882a593Smuzhiyun #include <linux/leds.h>
31*4882a593Smuzhiyun #include <linux/property.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include <asm/types.h>
34*4882a593Smuzhiyun #include <asm/setup.h>
35*4882a593Smuzhiyun #include <asm/memory.h>
36*4882a593Smuzhiyun #include <asm/mach-types.h>
37*4882a593Smuzhiyun #include <asm/irq.h>
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #include <asm/mach/arch.h>
40*4882a593Smuzhiyun #include <asm/mach/map.h>
41*4882a593Smuzhiyun #include <asm/mach/irq.h>
42*4882a593Smuzhiyun #include <asm/mach/flash.h>
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #include "pxa27x.h"
45*4882a593Smuzhiyun #include <linux/platform_data/mmc-pxamci.h>
46*4882a593Smuzhiyun #include "udc.h"
47*4882a593Smuzhiyun #include "pxa27x-udc.h"
48*4882a593Smuzhiyun #include <mach/smemc.h>
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #include <linux/spi/spi.h>
51*4882a593Smuzhiyun #include <linux/spi/pxa2xx_spi.h>
52*4882a593Smuzhiyun #include <linux/mfd/da903x.h>
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #include "devices.h"
55*4882a593Smuzhiyun #include "generic.h"
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define STARGATE_NR_IRQS	(IRQ_BOARD_START + 8)
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* Bluetooth */
60*4882a593Smuzhiyun #define SG2_BT_RESET		81
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* SD */
63*4882a593Smuzhiyun #define SG2_GPIO_nSD_DETECT	90
64*4882a593Smuzhiyun #define SG2_SD_POWER_ENABLE	89
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun static unsigned long sg2_im2_unified_pin_config[] __initdata = {
67*4882a593Smuzhiyun 	/* Device Identification for wakeup*/
68*4882a593Smuzhiyun 	GPIO102_GPIO,
69*4882a593Smuzhiyun 	/* DA9030 */
70*4882a593Smuzhiyun 	GPIO1_GPIO,
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	/* MMC */
73*4882a593Smuzhiyun 	GPIO32_MMC_CLK,
74*4882a593Smuzhiyun 	GPIO112_MMC_CMD,
75*4882a593Smuzhiyun 	GPIO92_MMC_DAT_0,
76*4882a593Smuzhiyun 	GPIO109_MMC_DAT_1,
77*4882a593Smuzhiyun 	GPIO110_MMC_DAT_2,
78*4882a593Smuzhiyun 	GPIO111_MMC_DAT_3,
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* 802.15.4 radio - driver out of mainline */
81*4882a593Smuzhiyun 	GPIO22_GPIO,			/* CC_RSTN */
82*4882a593Smuzhiyun 	GPIO114_GPIO,			/* CC_FIFO */
83*4882a593Smuzhiyun 	GPIO116_GPIO,			/* CC_CCA */
84*4882a593Smuzhiyun 	GPIO0_GPIO,			/* CC_FIFOP */
85*4882a593Smuzhiyun 	GPIO16_GPIO,			/* CCSFD */
86*4882a593Smuzhiyun 	GPIO115_GPIO,			/* Power enable */
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	/* I2C */
89*4882a593Smuzhiyun 	GPIO117_I2C_SCL,
90*4882a593Smuzhiyun 	GPIO118_I2C_SDA,
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	/* SSP 3 - 802.15.4 radio */
93*4882a593Smuzhiyun 	GPIO39_GPIO,			/* Chip Select */
94*4882a593Smuzhiyun 	GPIO34_SSP3_SCLK,
95*4882a593Smuzhiyun 	GPIO35_SSP3_TXD,
96*4882a593Smuzhiyun 	GPIO41_SSP3_RXD,
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	/* SSP 2 to daughter boards */
99*4882a593Smuzhiyun 	GPIO11_SSP2_RXD,
100*4882a593Smuzhiyun 	GPIO38_SSP2_TXD,
101*4882a593Smuzhiyun 	GPIO36_SSP2_SCLK,
102*4882a593Smuzhiyun 	GPIO37_GPIO, /* chip select */
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	/* SSP 1 - to daughter boards */
105*4882a593Smuzhiyun 	GPIO24_GPIO,			/* Chip Select */
106*4882a593Smuzhiyun 	GPIO23_SSP1_SCLK,
107*4882a593Smuzhiyun 	GPIO25_SSP1_TXD,
108*4882a593Smuzhiyun 	GPIO26_SSP1_RXD,
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	/* BTUART Basic Connector*/
111*4882a593Smuzhiyun 	GPIO42_BTUART_RXD,
112*4882a593Smuzhiyun 	GPIO43_BTUART_TXD,
113*4882a593Smuzhiyun 	GPIO44_BTUART_CTS,
114*4882a593Smuzhiyun 	GPIO45_BTUART_RTS,
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	/* STUART  - IM2 via debug board not sure on SG2*/
117*4882a593Smuzhiyun 	GPIO46_STUART_RXD,
118*4882a593Smuzhiyun 	GPIO47_STUART_TXD,
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/* Basic sensor board */
121*4882a593Smuzhiyun 	GPIO96_GPIO,	/* accelerometer interrupt */
122*4882a593Smuzhiyun 	GPIO99_GPIO,	/* ADC interrupt */
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* SHT15 */
125*4882a593Smuzhiyun 	GPIO100_GPIO,
126*4882a593Smuzhiyun 	GPIO98_GPIO,
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/* Basic sensor board */
129*4882a593Smuzhiyun 	GPIO96_GPIO,	/* accelerometer interrupt */
130*4882a593Smuzhiyun 	GPIO99_GPIO,	/* ADC interrupt */
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	/* Connector pins specified as gpios */
133*4882a593Smuzhiyun 	GPIO94_GPIO, /* large basic connector pin 14 */
134*4882a593Smuzhiyun 	GPIO10_GPIO, /* large basic connector pin 23 */
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static struct gpiod_lookup_table sht15_gpiod_table = {
138*4882a593Smuzhiyun 	.dev_id = "sht15",
139*4882a593Smuzhiyun 	.table = {
140*4882a593Smuzhiyun 		/* FIXME: should this have |GPIO_OPEN_DRAIN set? */
141*4882a593Smuzhiyun 		GPIO_LOOKUP("gpio-pxa", 100, "data", GPIO_ACTIVE_HIGH),
142*4882a593Smuzhiyun 		GPIO_LOOKUP("gpio-pxa", 98, "clk", GPIO_ACTIVE_HIGH),
143*4882a593Smuzhiyun 	},
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun static struct platform_device sht15 = {
147*4882a593Smuzhiyun 	.name = "sht15",
148*4882a593Smuzhiyun 	.id = -1,
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun static struct regulator_consumer_supply stargate2_sensor_3_con[] = {
152*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vcc", "sht15"),
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun enum stargate2_ldos{
156*4882a593Smuzhiyun 	vcc_vref,
157*4882a593Smuzhiyun 	vcc_cc2420,
158*4882a593Smuzhiyun 	/* a mote connector? */
159*4882a593Smuzhiyun 	vcc_mica,
160*4882a593Smuzhiyun 	/* the CSR bluecore chip */
161*4882a593Smuzhiyun 	vcc_bt,
162*4882a593Smuzhiyun 	/* The two voltages available to sensor boards */
163*4882a593Smuzhiyun 	vcc_sensor_1_8,
164*4882a593Smuzhiyun 	vcc_sensor_3,
165*4882a593Smuzhiyun 	/* directly connected to the pxa27x */
166*4882a593Smuzhiyun 	vcc_sram_ext,
167*4882a593Smuzhiyun 	vcc_pxa_pll,
168*4882a593Smuzhiyun 	vcc_pxa_usim, /* Reference voltage for certain gpios */
169*4882a593Smuzhiyun 	vcc_pxa_mem,
170*4882a593Smuzhiyun 	vcc_pxa_flash,
171*4882a593Smuzhiyun 	vcc_pxa_core, /*Dc-Dc buck not yet supported */
172*4882a593Smuzhiyun 	vcc_lcd,
173*4882a593Smuzhiyun 	vcc_bb,
174*4882a593Smuzhiyun 	vcc_bbio, /*not sure!*/
175*4882a593Smuzhiyun 	vcc_io, /* cc2420 802.15.4 radio and pxa vcc_io ?*/
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun /* The values of the various regulator constraints are obviously dependent
179*4882a593Smuzhiyun  * on exactly what is wired to each ldo.  Unfortunately this information is
180*4882a593Smuzhiyun  * not generally available.  More information has been requested from Xbow.
181*4882a593Smuzhiyun  */
182*4882a593Smuzhiyun static struct regulator_init_data stargate2_ldo_init_data[] = {
183*4882a593Smuzhiyun 	[vcc_bbio] = {
184*4882a593Smuzhiyun 		.constraints = { /* board default 1.8V */
185*4882a593Smuzhiyun 			.name = "vcc_bbio",
186*4882a593Smuzhiyun 			.min_uV = 1800000,
187*4882a593Smuzhiyun 			.max_uV = 1800000,
188*4882a593Smuzhiyun 		},
189*4882a593Smuzhiyun 	},
190*4882a593Smuzhiyun 	[vcc_bb] = {
191*4882a593Smuzhiyun 		.constraints = { /* board default 2.8V */
192*4882a593Smuzhiyun 			.name = "vcc_bb",
193*4882a593Smuzhiyun 			.min_uV = 2700000,
194*4882a593Smuzhiyun 			.max_uV = 3000000,
195*4882a593Smuzhiyun 		},
196*4882a593Smuzhiyun 	},
197*4882a593Smuzhiyun 	[vcc_pxa_flash] = {
198*4882a593Smuzhiyun 		.constraints = {/* default is 1.8V */
199*4882a593Smuzhiyun 			.name = "vcc_pxa_flash",
200*4882a593Smuzhiyun 			.min_uV = 1800000,
201*4882a593Smuzhiyun 			.max_uV = 1800000,
202*4882a593Smuzhiyun 		},
203*4882a593Smuzhiyun 	},
204*4882a593Smuzhiyun 	[vcc_cc2420] = { /* also vcc_io */
205*4882a593Smuzhiyun 		.constraints = {
206*4882a593Smuzhiyun 			/* board default is 2.8V */
207*4882a593Smuzhiyun 			.name = "vcc_cc2420",
208*4882a593Smuzhiyun 			.min_uV = 2700000,
209*4882a593Smuzhiyun 			.max_uV = 3300000,
210*4882a593Smuzhiyun 		},
211*4882a593Smuzhiyun 	},
212*4882a593Smuzhiyun 	[vcc_vref] = { /* Reference for what? */
213*4882a593Smuzhiyun 		.constraints = { /* default 1.8V */
214*4882a593Smuzhiyun 			.name = "vcc_vref",
215*4882a593Smuzhiyun 			.min_uV = 1800000,
216*4882a593Smuzhiyun 			.max_uV = 1800000,
217*4882a593Smuzhiyun 		},
218*4882a593Smuzhiyun 	},
219*4882a593Smuzhiyun 	[vcc_sram_ext] = {
220*4882a593Smuzhiyun 		.constraints = { /* default 2.8V */
221*4882a593Smuzhiyun 			.name = "vcc_sram_ext",
222*4882a593Smuzhiyun 			.min_uV = 2800000,
223*4882a593Smuzhiyun 			.max_uV = 2800000,
224*4882a593Smuzhiyun 		},
225*4882a593Smuzhiyun 	},
226*4882a593Smuzhiyun 	[vcc_mica] = {
227*4882a593Smuzhiyun 		.constraints = { /* default 2.8V */
228*4882a593Smuzhiyun 			.name = "vcc_mica",
229*4882a593Smuzhiyun 			.min_uV = 2800000,
230*4882a593Smuzhiyun 			.max_uV = 2800000,
231*4882a593Smuzhiyun 		},
232*4882a593Smuzhiyun 	},
233*4882a593Smuzhiyun 	[vcc_bt] = {
234*4882a593Smuzhiyun 		.constraints = { /* default 2.8V */
235*4882a593Smuzhiyun 			.name = "vcc_bt",
236*4882a593Smuzhiyun 			.min_uV = 2800000,
237*4882a593Smuzhiyun 			.max_uV = 2800000,
238*4882a593Smuzhiyun 		},
239*4882a593Smuzhiyun 	},
240*4882a593Smuzhiyun 	[vcc_lcd] = {
241*4882a593Smuzhiyun 		.constraints = { /* default 2.8V */
242*4882a593Smuzhiyun 			.name = "vcc_lcd",
243*4882a593Smuzhiyun 			.min_uV = 2700000,
244*4882a593Smuzhiyun 			.max_uV = 3300000,
245*4882a593Smuzhiyun 		},
246*4882a593Smuzhiyun 	},
247*4882a593Smuzhiyun 	[vcc_io] = { /* Same or higher than everything
248*4882a593Smuzhiyun 			  * bar vccbat and vccusb */
249*4882a593Smuzhiyun 		.constraints = { /* default 2.8V */
250*4882a593Smuzhiyun 			.name = "vcc_io",
251*4882a593Smuzhiyun 			.min_uV = 2692000,
252*4882a593Smuzhiyun 			.max_uV = 3300000,
253*4882a593Smuzhiyun 		},
254*4882a593Smuzhiyun 	},
255*4882a593Smuzhiyun 	[vcc_sensor_1_8] = {
256*4882a593Smuzhiyun 		.constraints = { /* default 1.8V */
257*4882a593Smuzhiyun 			.name = "vcc_sensor_1_8",
258*4882a593Smuzhiyun 			.min_uV = 1800000,
259*4882a593Smuzhiyun 			.max_uV = 1800000,
260*4882a593Smuzhiyun 		},
261*4882a593Smuzhiyun 	},
262*4882a593Smuzhiyun 	[vcc_sensor_3] = { /* curiously default 2.8V */
263*4882a593Smuzhiyun 		.constraints = {
264*4882a593Smuzhiyun 			.name = "vcc_sensor_3",
265*4882a593Smuzhiyun 			.min_uV = 2800000,
266*4882a593Smuzhiyun 			.max_uV = 3000000,
267*4882a593Smuzhiyun 		},
268*4882a593Smuzhiyun 		.num_consumer_supplies = ARRAY_SIZE(stargate2_sensor_3_con),
269*4882a593Smuzhiyun 		.consumer_supplies = stargate2_sensor_3_con,
270*4882a593Smuzhiyun 	},
271*4882a593Smuzhiyun 	[vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/
272*4882a593Smuzhiyun 		.constraints = {
273*4882a593Smuzhiyun 			.name = "vcc_pxa_pll",
274*4882a593Smuzhiyun 			.min_uV = 1170000,
275*4882a593Smuzhiyun 			.max_uV = 1430000,
276*4882a593Smuzhiyun 		},
277*4882a593Smuzhiyun 	},
278*4882a593Smuzhiyun 	[vcc_pxa_usim] = {
279*4882a593Smuzhiyun 		.constraints = { /* default 1.8V */
280*4882a593Smuzhiyun 			.name = "vcc_pxa_usim",
281*4882a593Smuzhiyun 			.min_uV = 1710000,
282*4882a593Smuzhiyun 			.max_uV = 2160000,
283*4882a593Smuzhiyun 		},
284*4882a593Smuzhiyun 	},
285*4882a593Smuzhiyun 	[vcc_pxa_mem] = {
286*4882a593Smuzhiyun 		.constraints = { /* default 1.8V */
287*4882a593Smuzhiyun 			.name = "vcc_pxa_mem",
288*4882a593Smuzhiyun 			.min_uV = 1800000,
289*4882a593Smuzhiyun 			.max_uV = 1800000,
290*4882a593Smuzhiyun 		},
291*4882a593Smuzhiyun 	},
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun static struct mtd_partition stargate2flash_partitions[] = {
295*4882a593Smuzhiyun 	{
296*4882a593Smuzhiyun 		.name = "Bootloader",
297*4882a593Smuzhiyun 		.size = 0x00040000,
298*4882a593Smuzhiyun 		.offset = 0,
299*4882a593Smuzhiyun 		.mask_flags = 0,
300*4882a593Smuzhiyun 	}, {
301*4882a593Smuzhiyun 		.name = "Kernel",
302*4882a593Smuzhiyun 		.size = 0x00200000,
303*4882a593Smuzhiyun 		.offset = 0x00040000,
304*4882a593Smuzhiyun 		.mask_flags = 0
305*4882a593Smuzhiyun 	}, {
306*4882a593Smuzhiyun 		.name = "Filesystem",
307*4882a593Smuzhiyun 		.size = 0x01DC0000,
308*4882a593Smuzhiyun 		.offset = 0x00240000,
309*4882a593Smuzhiyun 		.mask_flags = 0
310*4882a593Smuzhiyun 	},
311*4882a593Smuzhiyun };
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun static struct resource flash_resources = {
314*4882a593Smuzhiyun 	.start = PXA_CS0_PHYS,
315*4882a593Smuzhiyun 	.end = PXA_CS0_PHYS + SZ_32M - 1,
316*4882a593Smuzhiyun 	.flags = IORESOURCE_MEM,
317*4882a593Smuzhiyun };
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun static struct flash_platform_data stargate2_flash_data = {
320*4882a593Smuzhiyun 	.map_name = "cfi_probe",
321*4882a593Smuzhiyun 	.parts = stargate2flash_partitions,
322*4882a593Smuzhiyun 	.nr_parts = ARRAY_SIZE(stargate2flash_partitions),
323*4882a593Smuzhiyun 	.name = "PXA27xOnChipROM",
324*4882a593Smuzhiyun 	.width = 2,
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun static struct platform_device stargate2_flash_device = {
328*4882a593Smuzhiyun 	.name = "pxa2xx-flash",
329*4882a593Smuzhiyun 	.id = 0,
330*4882a593Smuzhiyun 	.dev = {
331*4882a593Smuzhiyun 		.platform_data = &stargate2_flash_data,
332*4882a593Smuzhiyun 	},
333*4882a593Smuzhiyun 	.resource = &flash_resources,
334*4882a593Smuzhiyun 	.num_resources = 1,
335*4882a593Smuzhiyun };
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun static struct pxa2xx_spi_controller pxa_ssp_master_0_info = {
338*4882a593Smuzhiyun 	.num_chipselect = 1,
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun static struct pxa2xx_spi_controller pxa_ssp_master_1_info = {
342*4882a593Smuzhiyun 	.num_chipselect = 1,
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun static struct pxa2xx_spi_controller pxa_ssp_master_2_info = {
346*4882a593Smuzhiyun 	.num_chipselect = 1,
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun /* An upcoming kernel change will scrap SFRM usage so these
350*4882a593Smuzhiyun  * drivers have been moved to use gpio's via cs_control */
351*4882a593Smuzhiyun static struct pxa2xx_spi_chip staccel_chip_info = {
352*4882a593Smuzhiyun 	.tx_threshold = 8,
353*4882a593Smuzhiyun 	.rx_threshold = 8,
354*4882a593Smuzhiyun 	.dma_burst_size = 8,
355*4882a593Smuzhiyun 	.timeout = 235,
356*4882a593Smuzhiyun 	.gpio_cs = 24,
357*4882a593Smuzhiyun };
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun static struct pxa2xx_spi_chip cc2420_info = {
360*4882a593Smuzhiyun 	.tx_threshold = 8,
361*4882a593Smuzhiyun 	.rx_threshold = 8,
362*4882a593Smuzhiyun 	.dma_burst_size = 8,
363*4882a593Smuzhiyun 	.timeout = 235,
364*4882a593Smuzhiyun 	.gpio_cs = 39,
365*4882a593Smuzhiyun };
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun static struct spi_board_info spi_board_info[] __initdata = {
368*4882a593Smuzhiyun 	{
369*4882a593Smuzhiyun 		.modalias = "lis3l02dq",
370*4882a593Smuzhiyun 		.max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */
371*4882a593Smuzhiyun 		.bus_num = 1,
372*4882a593Smuzhiyun 		.chip_select = 0,
373*4882a593Smuzhiyun 		.controller_data = &staccel_chip_info,
374*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(96),
375*4882a593Smuzhiyun 	}, {
376*4882a593Smuzhiyun 		.modalias = "cc2420",
377*4882a593Smuzhiyun 		.max_speed_hz = 6500000,
378*4882a593Smuzhiyun 		.bus_num = 3,
379*4882a593Smuzhiyun 		.chip_select = 0,
380*4882a593Smuzhiyun 		.controller_data = &cc2420_info,
381*4882a593Smuzhiyun 	},
382*4882a593Smuzhiyun };
383*4882a593Smuzhiyun 
sg2_udc_command(int cmd)384*4882a593Smuzhiyun static void sg2_udc_command(int cmd)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun 	switch (cmd) {
387*4882a593Smuzhiyun 	case PXA2XX_UDC_CMD_CONNECT:
388*4882a593Smuzhiyun 		UP2OCR |=  UP2OCR_HXOE  | UP2OCR_DPPUE | UP2OCR_DPPUBE;
389*4882a593Smuzhiyun 		break;
390*4882a593Smuzhiyun 	case PXA2XX_UDC_CMD_DISCONNECT:
391*4882a593Smuzhiyun 		UP2OCR &= ~(UP2OCR_HXOE  | UP2OCR_DPPUE | UP2OCR_DPPUBE);
392*4882a593Smuzhiyun 		break;
393*4882a593Smuzhiyun 	}
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun static struct i2c_pxa_platform_data i2c_pwr_pdata = {
397*4882a593Smuzhiyun 	.fast_mode = 1,
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun static struct i2c_pxa_platform_data i2c_pdata = {
401*4882a593Smuzhiyun 	.fast_mode = 1,
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun 
imote2_stargate2_init(void)404*4882a593Smuzhiyun static void __init imote2_stargate2_init(void)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(sg2_im2_unified_pin_config));
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	pxa_set_ffuart_info(NULL);
410*4882a593Smuzhiyun 	pxa_set_btuart_info(NULL);
411*4882a593Smuzhiyun 	pxa_set_stuart_info(NULL);
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info);
414*4882a593Smuzhiyun 	pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info);
415*4882a593Smuzhiyun 	pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info);
416*4882a593Smuzhiyun 	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	pxa27x_set_i2c_power_info(&i2c_pwr_pdata);
420*4882a593Smuzhiyun 	pxa_set_i2c_info(&i2c_pdata);
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun #ifdef CONFIG_MACH_INTELMOTE2
424*4882a593Smuzhiyun /* As the the imote2 doesn't currently have a conventional SD slot
425*4882a593Smuzhiyun  * there is no option to hotplug cards, making all this rather simple
426*4882a593Smuzhiyun  */
imote2_mci_get_ro(struct device * dev)427*4882a593Smuzhiyun static int imote2_mci_get_ro(struct device *dev)
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun 	return 0;
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun /* Rather simple case as hotplugging not possible */
433*4882a593Smuzhiyun static struct pxamci_platform_data imote2_mci_platform_data = {
434*4882a593Smuzhiyun 	.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */
435*4882a593Smuzhiyun 	.get_ro = imote2_mci_get_ro,
436*4882a593Smuzhiyun };
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun static struct gpio_led imote2_led_pins[] = {
439*4882a593Smuzhiyun 	{
440*4882a593Smuzhiyun 		.name       =  "imote2:red",
441*4882a593Smuzhiyun 		.gpio       = 103,
442*4882a593Smuzhiyun 		.active_low = 1,
443*4882a593Smuzhiyun 	}, {
444*4882a593Smuzhiyun 		.name       = "imote2:green",
445*4882a593Smuzhiyun 		.gpio       = 104,
446*4882a593Smuzhiyun 		.active_low = 1,
447*4882a593Smuzhiyun 	}, {
448*4882a593Smuzhiyun 		.name       = "imote2:blue",
449*4882a593Smuzhiyun 		.gpio       = 105,
450*4882a593Smuzhiyun 		.active_low = 1,
451*4882a593Smuzhiyun 	},
452*4882a593Smuzhiyun };
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun static struct gpio_led_platform_data imote2_led_data = {
455*4882a593Smuzhiyun 	.num_leds = ARRAY_SIZE(imote2_led_pins),
456*4882a593Smuzhiyun 	.leds     = imote2_led_pins,
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun static struct platform_device imote2_leds = {
460*4882a593Smuzhiyun 	.name = "leds-gpio",
461*4882a593Smuzhiyun 	.id   = -1,
462*4882a593Smuzhiyun 	.dev = {
463*4882a593Smuzhiyun 		.platform_data = &imote2_led_data,
464*4882a593Smuzhiyun 	},
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun static struct da903x_subdev_info imote2_da9030_subdevs[] = {
468*4882a593Smuzhiyun 	{
469*4882a593Smuzhiyun 		.name = "da903x-regulator",
470*4882a593Smuzhiyun 		.id = DA9030_ID_LDO2,
471*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_bbio],
472*4882a593Smuzhiyun 	}, {
473*4882a593Smuzhiyun 		.name = "da903x-regulator",
474*4882a593Smuzhiyun 		.id = DA9030_ID_LDO3,
475*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_bb],
476*4882a593Smuzhiyun 	}, {
477*4882a593Smuzhiyun 		.name = "da903x-regulator",
478*4882a593Smuzhiyun 		.id = DA9030_ID_LDO4,
479*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_pxa_flash],
480*4882a593Smuzhiyun 	}, {
481*4882a593Smuzhiyun 		.name = "da903x-regulator",
482*4882a593Smuzhiyun 		.id = DA9030_ID_LDO5,
483*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_cc2420],
484*4882a593Smuzhiyun 	}, {
485*4882a593Smuzhiyun 		.name = "da903x-regulator",
486*4882a593Smuzhiyun 		.id = DA9030_ID_LDO6,
487*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_vref],
488*4882a593Smuzhiyun 	}, {
489*4882a593Smuzhiyun 		.name = "da903x-regulator",
490*4882a593Smuzhiyun 		.id = DA9030_ID_LDO7,
491*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_sram_ext],
492*4882a593Smuzhiyun 	}, {
493*4882a593Smuzhiyun 		.name = "da903x-regulator",
494*4882a593Smuzhiyun 		.id = DA9030_ID_LDO8,
495*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_mica],
496*4882a593Smuzhiyun 	}, {
497*4882a593Smuzhiyun 		.name = "da903x-regulator",
498*4882a593Smuzhiyun 		.id = DA9030_ID_LDO9,
499*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_bt],
500*4882a593Smuzhiyun 	}, {
501*4882a593Smuzhiyun 		.name = "da903x-regulator",
502*4882a593Smuzhiyun 		.id = DA9030_ID_LDO10,
503*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_sensor_1_8],
504*4882a593Smuzhiyun 	}, {
505*4882a593Smuzhiyun 		.name = "da903x-regulator",
506*4882a593Smuzhiyun 		.id = DA9030_ID_LDO11,
507*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_sensor_3],
508*4882a593Smuzhiyun 	}, {
509*4882a593Smuzhiyun 		.name = "da903x-regulator",
510*4882a593Smuzhiyun 		.id = DA9030_ID_LDO12,
511*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_lcd],
512*4882a593Smuzhiyun 	}, {
513*4882a593Smuzhiyun 		.name = "da903x-regulator",
514*4882a593Smuzhiyun 		.id = DA9030_ID_LDO15,
515*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_pxa_pll],
516*4882a593Smuzhiyun 	}, {
517*4882a593Smuzhiyun 		.name = "da903x-regulator",
518*4882a593Smuzhiyun 		.id = DA9030_ID_LDO17,
519*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_pxa_usim],
520*4882a593Smuzhiyun 	}, {
521*4882a593Smuzhiyun 		.name = "da903x-regulator", /*pxa vcc i/o and cc2420 vcc i/o */
522*4882a593Smuzhiyun 		.id = DA9030_ID_LDO18,
523*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_io],
524*4882a593Smuzhiyun 	}, {
525*4882a593Smuzhiyun 		.name = "da903x-regulator",
526*4882a593Smuzhiyun 		.id = DA9030_ID_LDO19,
527*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_pxa_mem],
528*4882a593Smuzhiyun 	},
529*4882a593Smuzhiyun };
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun static struct da903x_platform_data imote2_da9030_pdata = {
532*4882a593Smuzhiyun 	.num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs),
533*4882a593Smuzhiyun 	.subdevs = imote2_da9030_subdevs,
534*4882a593Smuzhiyun };
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = {
537*4882a593Smuzhiyun 	{
538*4882a593Smuzhiyun 		.type = "da9030",
539*4882a593Smuzhiyun 		.addr = 0x49,
540*4882a593Smuzhiyun 		.platform_data = &imote2_da9030_pdata,
541*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(1),
542*4882a593Smuzhiyun 	},
543*4882a593Smuzhiyun };
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun static struct i2c_board_info __initdata imote2_i2c_board_info[] = {
546*4882a593Smuzhiyun 	{ /* UCAM sensor board */
547*4882a593Smuzhiyun 		.type = "max1239",
548*4882a593Smuzhiyun 		.addr = 0x35,
549*4882a593Smuzhiyun 	}, { /* ITS400 Sensor board only */
550*4882a593Smuzhiyun 		.type = "max1363",
551*4882a593Smuzhiyun 		.addr = 0x34,
552*4882a593Smuzhiyun 		/* Through a nand gate - Also beware, on V2 sensor board the
553*4882a593Smuzhiyun 		 * pull up resistors are missing.
554*4882a593Smuzhiyun 		 */
555*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(99),
556*4882a593Smuzhiyun 	}, { /* ITS400 Sensor board only */
557*4882a593Smuzhiyun 		.type = "tsl2561",
558*4882a593Smuzhiyun 		.addr = 0x49,
559*4882a593Smuzhiyun 		/* Through a nand gate - Also beware, on V2 sensor board the
560*4882a593Smuzhiyun 		 * pull up resistors are missing.
561*4882a593Smuzhiyun 		 */
562*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(99),
563*4882a593Smuzhiyun 	}, { /* ITS400 Sensor board only */
564*4882a593Smuzhiyun 		.type = "tmp175",
565*4882a593Smuzhiyun 		.addr = 0x4A,
566*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(96),
567*4882a593Smuzhiyun 	}, { /* IMB400 Multimedia board */
568*4882a593Smuzhiyun 		.type = "wm8940",
569*4882a593Smuzhiyun 		.addr = 0x1A,
570*4882a593Smuzhiyun 	},
571*4882a593Smuzhiyun };
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun static unsigned long imote2_pin_config[] __initdata = {
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	/* Button */
576*4882a593Smuzhiyun 	GPIO91_GPIO,
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	/* LEDS */
579*4882a593Smuzhiyun 	GPIO103_GPIO, /* red led */
580*4882a593Smuzhiyun 	GPIO104_GPIO, /* green led */
581*4882a593Smuzhiyun 	GPIO105_GPIO, /* blue led */
582*4882a593Smuzhiyun };
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = {
585*4882a593Smuzhiyun 	.udc_command		= sg2_udc_command,
586*4882a593Smuzhiyun };
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun static struct platform_device imote2_audio_device = {
589*4882a593Smuzhiyun 	.name = "imote2-audio",
590*4882a593Smuzhiyun 	.id   = -1,
591*4882a593Smuzhiyun };
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun static struct platform_device *imote2_devices[] = {
594*4882a593Smuzhiyun 	&stargate2_flash_device,
595*4882a593Smuzhiyun 	&imote2_leds,
596*4882a593Smuzhiyun 	&sht15,
597*4882a593Smuzhiyun 	&imote2_audio_device,
598*4882a593Smuzhiyun };
599*4882a593Smuzhiyun 
imote2_init(void)600*4882a593Smuzhiyun static void __init imote2_init(void)
601*4882a593Smuzhiyun {
602*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config));
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	imote2_stargate2_init();
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	gpiod_add_lookup_table(&sht15_gpiod_table);
607*4882a593Smuzhiyun 	platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices));
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	i2c_register_board_info(0, imote2_i2c_board_info,
610*4882a593Smuzhiyun 				ARRAY_SIZE(imote2_i2c_board_info));
611*4882a593Smuzhiyun 	i2c_register_board_info(1, imote2_pwr_i2c_board_info,
612*4882a593Smuzhiyun 				ARRAY_SIZE(imote2_pwr_i2c_board_info));
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	pxa_set_mci_info(&imote2_mci_platform_data);
615*4882a593Smuzhiyun 	pxa_set_udc_info(&imote2_udc_info);
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun #endif
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun #ifdef CONFIG_MACH_STARGATE2
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun static unsigned long stargate2_pin_config[] __initdata = {
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	GPIO15_nCS_1, /* SRAM */
624*4882a593Smuzhiyun 	/* SMC91x */
625*4882a593Smuzhiyun 	GPIO80_nCS_4,
626*4882a593Smuzhiyun 	GPIO40_GPIO, /*cable detect?*/
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	/* Button */
629*4882a593Smuzhiyun 	GPIO91_GPIO | WAKEUP_ON_LEVEL_HIGH,
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	/* Compact Flash */
632*4882a593Smuzhiyun 	GPIO79_PSKTSEL,
633*4882a593Smuzhiyun 	GPIO48_nPOE,
634*4882a593Smuzhiyun 	GPIO49_nPWE,
635*4882a593Smuzhiyun 	GPIO50_nPIOR,
636*4882a593Smuzhiyun 	GPIO51_nPIOW,
637*4882a593Smuzhiyun 	GPIO85_nPCE_1,
638*4882a593Smuzhiyun 	GPIO54_nPCE_2,
639*4882a593Smuzhiyun 	GPIO55_nPREG,
640*4882a593Smuzhiyun 	GPIO56_nPWAIT,
641*4882a593Smuzhiyun 	GPIO57_nIOIS16,
642*4882a593Smuzhiyun 	GPIO120_GPIO, /* Buff ctrl */
643*4882a593Smuzhiyun 	GPIO108_GPIO, /* Power ctrl */
644*4882a593Smuzhiyun 	GPIO82_GPIO, /* Reset */
645*4882a593Smuzhiyun 	GPIO53_GPIO, /* SG2_S0_GPIO_DETECT */
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	/* MMC not shared with imote2 */
648*4882a593Smuzhiyun 	GPIO90_GPIO, /* nSD detect */
649*4882a593Smuzhiyun 	GPIO89_GPIO, /* SD_POWER_ENABLE */
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	/* Bluetooth */
652*4882a593Smuzhiyun 	GPIO81_GPIO, /* reset */
653*4882a593Smuzhiyun };
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun static struct resource smc91x_resources[] = {
656*4882a593Smuzhiyun 	[0] = {
657*4882a593Smuzhiyun 		.name = "smc91x-regs",
658*4882a593Smuzhiyun 		.start = (PXA_CS4_PHYS + 0x300),
659*4882a593Smuzhiyun 		.end = (PXA_CS4_PHYS + 0xfffff),
660*4882a593Smuzhiyun 		.flags = IORESOURCE_MEM,
661*4882a593Smuzhiyun 	},
662*4882a593Smuzhiyun 	[1] = {
663*4882a593Smuzhiyun 		.start = PXA_GPIO_TO_IRQ(40),
664*4882a593Smuzhiyun 		.end = PXA_GPIO_TO_IRQ(40),
665*4882a593Smuzhiyun 		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
666*4882a593Smuzhiyun 	}
667*4882a593Smuzhiyun };
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun static struct smc91x_platdata stargate2_smc91x_info = {
670*4882a593Smuzhiyun 	.flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT
671*4882a593Smuzhiyun 	| SMC91X_NOWAIT | SMC91X_USE_DMA,
672*4882a593Smuzhiyun 	.pxa_u16_align4 = true,
673*4882a593Smuzhiyun };
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun static struct platform_device smc91x_device = {
676*4882a593Smuzhiyun 	.name = "smc91x",
677*4882a593Smuzhiyun 	.id = -1,
678*4882a593Smuzhiyun 	.num_resources = ARRAY_SIZE(smc91x_resources),
679*4882a593Smuzhiyun 	.resource = smc91x_resources,
680*4882a593Smuzhiyun 	.dev = {
681*4882a593Smuzhiyun 		.platform_data = &stargate2_smc91x_info,
682*4882a593Smuzhiyun 	},
683*4882a593Smuzhiyun };
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun /*
687*4882a593Smuzhiyun  * The card detect interrupt isn't debounced so we delay it by 250ms
688*4882a593Smuzhiyun  * to give the card a chance to fully insert / eject.
689*4882a593Smuzhiyun  */
stargate2_mci_init(struct device * dev,irq_handler_t stargate2_detect_int,void * data)690*4882a593Smuzhiyun static int stargate2_mci_init(struct device *dev,
691*4882a593Smuzhiyun 			      irq_handler_t stargate2_detect_int,
692*4882a593Smuzhiyun 			      void *data)
693*4882a593Smuzhiyun {
694*4882a593Smuzhiyun 	int err;
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 	err = gpio_request(SG2_SD_POWER_ENABLE, "SG2_sd_power_enable");
697*4882a593Smuzhiyun 	if (err) {
698*4882a593Smuzhiyun 		printk(KERN_ERR "Can't get the gpio for SD power control");
699*4882a593Smuzhiyun 		goto return_err;
700*4882a593Smuzhiyun 	}
701*4882a593Smuzhiyun 	gpio_direction_output(SG2_SD_POWER_ENABLE, 0);
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	err = gpio_request(SG2_GPIO_nSD_DETECT, "SG2_sd_detect");
704*4882a593Smuzhiyun 	if (err) {
705*4882a593Smuzhiyun 		printk(KERN_ERR "Can't get the sd detect gpio");
706*4882a593Smuzhiyun 		goto free_power_en;
707*4882a593Smuzhiyun 	}
708*4882a593Smuzhiyun 	gpio_direction_input(SG2_GPIO_nSD_DETECT);
709*4882a593Smuzhiyun 
710*4882a593Smuzhiyun 	err = request_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT),
711*4882a593Smuzhiyun 			  stargate2_detect_int,
712*4882a593Smuzhiyun 			  IRQ_TYPE_EDGE_BOTH,
713*4882a593Smuzhiyun 			  "MMC card detect",
714*4882a593Smuzhiyun 			  data);
715*4882a593Smuzhiyun 	if (err) {
716*4882a593Smuzhiyun 		printk(KERN_ERR "can't request MMC card detect IRQ\n");
717*4882a593Smuzhiyun 		goto free_nsd_detect;
718*4882a593Smuzhiyun 	}
719*4882a593Smuzhiyun 	return 0;
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun  free_nsd_detect:
722*4882a593Smuzhiyun 	gpio_free(SG2_GPIO_nSD_DETECT);
723*4882a593Smuzhiyun  free_power_en:
724*4882a593Smuzhiyun 	gpio_free(SG2_SD_POWER_ENABLE);
725*4882a593Smuzhiyun  return_err:
726*4882a593Smuzhiyun 	return err;
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun /**
730*4882a593Smuzhiyun  * stargate2_mci_setpower() - set state of mmc power supply
731*4882a593Smuzhiyun  *
732*4882a593Smuzhiyun  * Very simple control. Either it is on or off and is controlled by
733*4882a593Smuzhiyun  * a gpio pin */
stargate2_mci_setpower(struct device * dev,unsigned int vdd)734*4882a593Smuzhiyun static int stargate2_mci_setpower(struct device *dev, unsigned int vdd)
735*4882a593Smuzhiyun {
736*4882a593Smuzhiyun 	gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd);
737*4882a593Smuzhiyun 	return 0;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun 
stargate2_mci_exit(struct device * dev,void * data)740*4882a593Smuzhiyun static void stargate2_mci_exit(struct device *dev, void *data)
741*4882a593Smuzhiyun {
742*4882a593Smuzhiyun 	free_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT), data);
743*4882a593Smuzhiyun 	gpio_free(SG2_SD_POWER_ENABLE);
744*4882a593Smuzhiyun 	gpio_free(SG2_GPIO_nSD_DETECT);
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun static struct pxamci_platform_data stargate2_mci_platform_data = {
748*4882a593Smuzhiyun 	.detect_delay_ms = 250,
749*4882a593Smuzhiyun 	.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
750*4882a593Smuzhiyun 	.init = stargate2_mci_init,
751*4882a593Smuzhiyun 	.setpower = stargate2_mci_setpower,
752*4882a593Smuzhiyun 	.exit = stargate2_mci_exit,
753*4882a593Smuzhiyun };
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun /*
757*4882a593Smuzhiyun  * SRAM - The Stargate 2 has 32MB of SRAM.
758*4882a593Smuzhiyun  *
759*4882a593Smuzhiyun  * Here it is made available as an MTD. This will then
760*4882a593Smuzhiyun  * typically have a cifs filesystem created on it to provide
761*4882a593Smuzhiyun  * fast temporary storage.
762*4882a593Smuzhiyun  */
763*4882a593Smuzhiyun static struct resource sram_resources = {
764*4882a593Smuzhiyun 	.start = PXA_CS1_PHYS,
765*4882a593Smuzhiyun 	.end = PXA_CS1_PHYS + SZ_32M-1,
766*4882a593Smuzhiyun 	.flags = IORESOURCE_MEM,
767*4882a593Smuzhiyun };
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun static struct platdata_mtd_ram stargate2_sram_pdata = {
770*4882a593Smuzhiyun 	.mapname = "Stargate2 SRAM",
771*4882a593Smuzhiyun 	.bankwidth = 2,
772*4882a593Smuzhiyun };
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun static struct platform_device stargate2_sram = {
775*4882a593Smuzhiyun 	.name = "mtd-ram",
776*4882a593Smuzhiyun 	.id = 0,
777*4882a593Smuzhiyun 	.resource = &sram_resources,
778*4882a593Smuzhiyun 	.num_resources = 1,
779*4882a593Smuzhiyun 	.dev = {
780*4882a593Smuzhiyun 		.platform_data = &stargate2_sram_pdata,
781*4882a593Smuzhiyun 	},
782*4882a593Smuzhiyun };
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun static struct pcf857x_platform_data platform_data_pcf857x = {
785*4882a593Smuzhiyun 	.gpio_base = 128,
786*4882a593Smuzhiyun 	.n_latch = 0,
787*4882a593Smuzhiyun 	.setup = NULL,
788*4882a593Smuzhiyun 	.teardown = NULL,
789*4882a593Smuzhiyun 	.context = NULL,
790*4882a593Smuzhiyun };
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun static const struct property_entry pca9500_eeprom_properties[] = {
793*4882a593Smuzhiyun 	PROPERTY_ENTRY_U32("pagesize", 4),
794*4882a593Smuzhiyun 	{ }
795*4882a593Smuzhiyun };
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun /**
798*4882a593Smuzhiyun  * stargate2_reset_bluetooth() reset the bluecore to ensure consistent state
799*4882a593Smuzhiyun  **/
stargate2_reset_bluetooth(void)800*4882a593Smuzhiyun static int stargate2_reset_bluetooth(void)
801*4882a593Smuzhiyun {
802*4882a593Smuzhiyun 	int err;
803*4882a593Smuzhiyun 	err = gpio_request(SG2_BT_RESET, "SG2_BT_RESET");
804*4882a593Smuzhiyun 	if (err) {
805*4882a593Smuzhiyun 		printk(KERN_ERR "Could not get gpio for bluetooth reset\n");
806*4882a593Smuzhiyun 		return err;
807*4882a593Smuzhiyun 	}
808*4882a593Smuzhiyun 	gpio_direction_output(SG2_BT_RESET, 1);
809*4882a593Smuzhiyun 	mdelay(5);
810*4882a593Smuzhiyun 	/* now reset it - 5 msec minimum */
811*4882a593Smuzhiyun 	gpio_set_value(SG2_BT_RESET, 0);
812*4882a593Smuzhiyun 	mdelay(10);
813*4882a593Smuzhiyun 	gpio_set_value(SG2_BT_RESET, 1);
814*4882a593Smuzhiyun 	gpio_free(SG2_BT_RESET);
815*4882a593Smuzhiyun 	return 0;
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun 
818*4882a593Smuzhiyun static struct led_info stargate2_leds[] = {
819*4882a593Smuzhiyun 	{
820*4882a593Smuzhiyun 		.name = "sg2:red",
821*4882a593Smuzhiyun 		.flags = DA9030_LED_RATE_ON,
822*4882a593Smuzhiyun 	}, {
823*4882a593Smuzhiyun 		.name = "sg2:blue",
824*4882a593Smuzhiyun 		.flags = DA9030_LED_RATE_ON,
825*4882a593Smuzhiyun 	}, {
826*4882a593Smuzhiyun 		.name = "sg2:green",
827*4882a593Smuzhiyun 		.flags = DA9030_LED_RATE_ON,
828*4882a593Smuzhiyun 	},
829*4882a593Smuzhiyun };
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun static struct da903x_subdev_info stargate2_da9030_subdevs[] = {
832*4882a593Smuzhiyun 	{
833*4882a593Smuzhiyun 		.name = "da903x-led",
834*4882a593Smuzhiyun 		.id = DA9030_ID_LED_2,
835*4882a593Smuzhiyun 		.platform_data = &stargate2_leds[0],
836*4882a593Smuzhiyun 	}, {
837*4882a593Smuzhiyun 		.name = "da903x-led",
838*4882a593Smuzhiyun 		.id = DA9030_ID_LED_3,
839*4882a593Smuzhiyun 		.platform_data = &stargate2_leds[2],
840*4882a593Smuzhiyun 	}, {
841*4882a593Smuzhiyun 		.name = "da903x-led",
842*4882a593Smuzhiyun 		.id = DA9030_ID_LED_4,
843*4882a593Smuzhiyun 		.platform_data = &stargate2_leds[1],
844*4882a593Smuzhiyun 	}, {
845*4882a593Smuzhiyun 		.name = "da903x-regulator",
846*4882a593Smuzhiyun 		.id = DA9030_ID_LDO2,
847*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_bbio],
848*4882a593Smuzhiyun 	}, {
849*4882a593Smuzhiyun 		.name = "da903x-regulator",
850*4882a593Smuzhiyun 		.id = DA9030_ID_LDO3,
851*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_bb],
852*4882a593Smuzhiyun 	}, {
853*4882a593Smuzhiyun 		.name = "da903x-regulator",
854*4882a593Smuzhiyun 		.id = DA9030_ID_LDO4,
855*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_pxa_flash],
856*4882a593Smuzhiyun 	}, {
857*4882a593Smuzhiyun 		.name = "da903x-regulator",
858*4882a593Smuzhiyun 		.id = DA9030_ID_LDO5,
859*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_cc2420],
860*4882a593Smuzhiyun 	}, {
861*4882a593Smuzhiyun 		.name = "da903x-regulator",
862*4882a593Smuzhiyun 		.id = DA9030_ID_LDO6,
863*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_vref],
864*4882a593Smuzhiyun 	}, {
865*4882a593Smuzhiyun 		.name = "da903x-regulator",
866*4882a593Smuzhiyun 		.id = DA9030_ID_LDO7,
867*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_sram_ext],
868*4882a593Smuzhiyun 	}, {
869*4882a593Smuzhiyun 		.name = "da903x-regulator",
870*4882a593Smuzhiyun 		.id = DA9030_ID_LDO8,
871*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_mica],
872*4882a593Smuzhiyun 	}, {
873*4882a593Smuzhiyun 		.name = "da903x-regulator",
874*4882a593Smuzhiyun 		.id = DA9030_ID_LDO9,
875*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_bt],
876*4882a593Smuzhiyun 	}, {
877*4882a593Smuzhiyun 		.name = "da903x-regulator",
878*4882a593Smuzhiyun 		.id = DA9030_ID_LDO10,
879*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_sensor_1_8],
880*4882a593Smuzhiyun 	}, {
881*4882a593Smuzhiyun 		.name = "da903x-regulator",
882*4882a593Smuzhiyun 		.id = DA9030_ID_LDO11,
883*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_sensor_3],
884*4882a593Smuzhiyun 	}, {
885*4882a593Smuzhiyun 		.name = "da903x-regulator",
886*4882a593Smuzhiyun 		.id = DA9030_ID_LDO12,
887*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_lcd],
888*4882a593Smuzhiyun 	}, {
889*4882a593Smuzhiyun 		.name = "da903x-regulator",
890*4882a593Smuzhiyun 		.id = DA9030_ID_LDO15,
891*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_pxa_pll],
892*4882a593Smuzhiyun 	}, {
893*4882a593Smuzhiyun 		.name = "da903x-regulator",
894*4882a593Smuzhiyun 		.id = DA9030_ID_LDO17,
895*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_pxa_usim],
896*4882a593Smuzhiyun 	}, {
897*4882a593Smuzhiyun 		.name = "da903x-regulator", /*pxa vcc i/o and cc2420 vcc i/o */
898*4882a593Smuzhiyun 		.id = DA9030_ID_LDO18,
899*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_io],
900*4882a593Smuzhiyun 	}, {
901*4882a593Smuzhiyun 		.name = "da903x-regulator",
902*4882a593Smuzhiyun 		.id = DA9030_ID_LDO19,
903*4882a593Smuzhiyun 		.platform_data = &stargate2_ldo_init_data[vcc_pxa_mem],
904*4882a593Smuzhiyun 	},
905*4882a593Smuzhiyun };
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun static struct da903x_platform_data stargate2_da9030_pdata = {
908*4882a593Smuzhiyun 	.num_subdevs = ARRAY_SIZE(stargate2_da9030_subdevs),
909*4882a593Smuzhiyun 	.subdevs = stargate2_da9030_subdevs,
910*4882a593Smuzhiyun };
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = {
913*4882a593Smuzhiyun 	{
914*4882a593Smuzhiyun 		.type = "da9030",
915*4882a593Smuzhiyun 		.addr = 0x49,
916*4882a593Smuzhiyun 		.platform_data = &stargate2_da9030_pdata,
917*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(1),
918*4882a593Smuzhiyun 	},
919*4882a593Smuzhiyun };
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun static struct i2c_board_info __initdata stargate2_i2c_board_info[] = {
922*4882a593Smuzhiyun 	/* Techically this a pca9500 - but it's compatible with the 8574
923*4882a593Smuzhiyun 	 * for gpio expansion and the 24c02 for eeprom access.
924*4882a593Smuzhiyun 	 */
925*4882a593Smuzhiyun 	{
926*4882a593Smuzhiyun 		.type = "pcf8574",
927*4882a593Smuzhiyun 		.addr =  0x27,
928*4882a593Smuzhiyun 		.platform_data = &platform_data_pcf857x,
929*4882a593Smuzhiyun 	}, {
930*4882a593Smuzhiyun 		.type = "24c02",
931*4882a593Smuzhiyun 		.addr = 0x57,
932*4882a593Smuzhiyun 		.properties = pca9500_eeprom_properties,
933*4882a593Smuzhiyun 	}, {
934*4882a593Smuzhiyun 		.type = "max1238",
935*4882a593Smuzhiyun 		.addr = 0x35,
936*4882a593Smuzhiyun 	}, { /* ITS400 Sensor board only */
937*4882a593Smuzhiyun 		.type = "max1363",
938*4882a593Smuzhiyun 		.addr = 0x34,
939*4882a593Smuzhiyun 		/* Through a nand gate - Also beware, on V2 sensor board the
940*4882a593Smuzhiyun 		 * pull up resistors are missing.
941*4882a593Smuzhiyun 		 */
942*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(99),
943*4882a593Smuzhiyun 	}, { /* ITS400 Sensor board only */
944*4882a593Smuzhiyun 		.type = "tsl2561",
945*4882a593Smuzhiyun 		.addr = 0x49,
946*4882a593Smuzhiyun 		/* Through a nand gate - Also beware, on V2 sensor board the
947*4882a593Smuzhiyun 		 * pull up resistors are missing.
948*4882a593Smuzhiyun 		 */
949*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(99),
950*4882a593Smuzhiyun 	}, { /* ITS400 Sensor board only */
951*4882a593Smuzhiyun 		.type = "tmp175",
952*4882a593Smuzhiyun 		.addr = 0x4A,
953*4882a593Smuzhiyun 		.irq = PXA_GPIO_TO_IRQ(96),
954*4882a593Smuzhiyun 	},
955*4882a593Smuzhiyun };
956*4882a593Smuzhiyun 
957*4882a593Smuzhiyun /* Board doesn't support cable detection - so always lie and say
958*4882a593Smuzhiyun  * something is there.
959*4882a593Smuzhiyun  */
sg2_udc_detect(void)960*4882a593Smuzhiyun static int sg2_udc_detect(void)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun 	return 1;
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun 
965*4882a593Smuzhiyun static struct pxa2xx_udc_mach_info stargate2_udc_info __initdata = {
966*4882a593Smuzhiyun 	.udc_is_connected	= sg2_udc_detect,
967*4882a593Smuzhiyun 	.udc_command		= sg2_udc_command,
968*4882a593Smuzhiyun };
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun static struct platform_device *stargate2_devices[] = {
971*4882a593Smuzhiyun 	&stargate2_flash_device,
972*4882a593Smuzhiyun 	&stargate2_sram,
973*4882a593Smuzhiyun 	&smc91x_device,
974*4882a593Smuzhiyun 	&sht15,
975*4882a593Smuzhiyun };
976*4882a593Smuzhiyun 
stargate2_init(void)977*4882a593Smuzhiyun static void __init stargate2_init(void)
978*4882a593Smuzhiyun {
979*4882a593Smuzhiyun 	/* This is probably a board specific hack as this must be set
980*4882a593Smuzhiyun 	   prior to connecting the MFP stuff up. */
981*4882a593Smuzhiyun 	__raw_writel(__raw_readl(MECR) & ~MECR_NOS, MECR);
982*4882a593Smuzhiyun 
983*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config));
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	imote2_stargate2_init();
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 	gpiod_add_lookup_table(&sht15_gpiod_table);
988*4882a593Smuzhiyun 	platform_add_devices(ARRAY_AND_SIZE(stargate2_devices));
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 	i2c_register_board_info(0, ARRAY_AND_SIZE(stargate2_i2c_board_info));
991*4882a593Smuzhiyun 	i2c_register_board_info(1, stargate2_pwr_i2c_board_info,
992*4882a593Smuzhiyun 				ARRAY_SIZE(stargate2_pwr_i2c_board_info));
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun 	pxa_set_mci_info(&stargate2_mci_platform_data);
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun 	pxa_set_udc_info(&stargate2_udc_info);
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	stargate2_reset_bluetooth();
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun #endif
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun #ifdef CONFIG_MACH_INTELMOTE2
1003*4882a593Smuzhiyun MACHINE_START(INTELMOTE2, "IMOTE 2")
1004*4882a593Smuzhiyun 	.map_io		= pxa27x_map_io,
1005*4882a593Smuzhiyun 	.nr_irqs	= PXA_NR_IRQS,
1006*4882a593Smuzhiyun 	.init_irq	= pxa27x_init_irq,
1007*4882a593Smuzhiyun 	.handle_irq	= pxa27x_handle_irq,
1008*4882a593Smuzhiyun 	.init_time	= pxa_timer_init,
1009*4882a593Smuzhiyun 	.init_machine	= imote2_init,
1010*4882a593Smuzhiyun 	.atag_offset	= 0x100,
1011*4882a593Smuzhiyun 	.restart	= pxa_restart,
1012*4882a593Smuzhiyun MACHINE_END
1013*4882a593Smuzhiyun #endif
1014*4882a593Smuzhiyun 
1015*4882a593Smuzhiyun #ifdef CONFIG_MACH_STARGATE2
1016*4882a593Smuzhiyun MACHINE_START(STARGATE2, "Stargate 2")
1017*4882a593Smuzhiyun 	.map_io = pxa27x_map_io,
1018*4882a593Smuzhiyun 	.nr_irqs = STARGATE_NR_IRQS,
1019*4882a593Smuzhiyun 	.init_irq = pxa27x_init_irq,
1020*4882a593Smuzhiyun 	.handle_irq = pxa27x_handle_irq,
1021*4882a593Smuzhiyun 	.init_time	= pxa_timer_init,
1022*4882a593Smuzhiyun 	.init_machine = stargate2_init,
1023*4882a593Smuzhiyun 	.atag_offset = 0x100,
1024*4882a593Smuzhiyun 	.restart	= pxa_restart,
1025*4882a593Smuzhiyun MACHINE_END
1026*4882a593Smuzhiyun #endif
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