1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * PXA27x standby mode 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: David Burrage 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * 2005 (c) MontaVista Software, Inc. This file is licensed under 7*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program 8*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express 9*4882a593Smuzhiyun * or implied. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include <linux/linkage.h> 13*4882a593Smuzhiyun#include <asm/assembler.h> 14*4882a593Smuzhiyun#include <mach/hardware.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#include <mach/pxa2xx-regs.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun .text 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun#ifdef CONFIG_PXA27x 21*4882a593SmuzhiyunENTRY(pxa_cpu_standby) 22*4882a593Smuzhiyun ldr r0, =PSSR 23*4882a593Smuzhiyun mov r1, #(PSSR_PH | PSSR_STS) 24*4882a593Smuzhiyun mov r2, #PWRMODE_STANDBY 25*4882a593Smuzhiyun mov r3, #UNCACHED_PHYS_0 @ Read mem context in. 26*4882a593Smuzhiyun ldr ip, [r3] 27*4882a593Smuzhiyun b 1f 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun .align 5 30*4882a593Smuzhiyun1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby 31*4882a593Smuzhiyun str r1, [r0] @ make sure PSSR_PH/STS are clear 32*4882a593Smuzhiyun ret lr 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun#endif 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun#ifdef CONFIG_PXA3xx 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun#define PXA3_MDCNFG 0x0000 39*4882a593Smuzhiyun#define PXA3_MDCNFG_DMCEN (1 << 30) 40*4882a593Smuzhiyun#define PXA3_DDR_HCAL 0x0060 41*4882a593Smuzhiyun#define PXA3_DDR_HCAL_HCRNG 0x1f 42*4882a593Smuzhiyun#define PXA3_DDR_HCAL_HCPROG (1 << 28) 43*4882a593Smuzhiyun#define PXA3_DDR_HCAL_HCEN (1 << 31) 44*4882a593Smuzhiyun#define PXA3_DMCIER 0x0070 45*4882a593Smuzhiyun#define PXA3_DMCIER_EDLP (1 << 29) 46*4882a593Smuzhiyun#define PXA3_DMCISR 0x0078 47*4882a593Smuzhiyun#define PXA3_RCOMP 0x0100 48*4882a593Smuzhiyun#define PXA3_RCOMP_SWEVAL (1 << 31) 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunENTRY(pm_enter_standby_start) 51*4882a593Smuzhiyun mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG) 52*4882a593Smuzhiyun add r1, r1, #0x00100000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Preload the TLB entry for accessing the dynamic memory 56*4882a593Smuzhiyun * controller registers. Note that page table lookups will 57*4882a593Smuzhiyun * fail until the dynamic memory controller has been 58*4882a593Smuzhiyun * reinitialised - and that includes MMU page table walks. 59*4882a593Smuzhiyun * This also means that only the dynamic memory controller 60*4882a593Smuzhiyun * can be reliably accessed in the code following standby. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun ldr r2, [r1] @ Dummy read PXA3_MDCNFG 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun mcr p14, 0, r0, c7, c0, 0 65*4882a593Smuzhiyun .rept 8 66*4882a593Smuzhiyun nop 67*4882a593Smuzhiyun .endr 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN 70*4882a593Smuzhiyun bic r0, r0, #PXA3_DDR_HCAL_HCEN 71*4882a593Smuzhiyun str r0, [r1, #PXA3_DDR_HCAL] 72*4882a593Smuzhiyun1: ldr r0, [r1, #PXA3_DDR_HCAL] 73*4882a593Smuzhiyun tst r0, #PXA3_DDR_HCAL_HCEN 74*4882a593Smuzhiyun bne 1b 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP 77*4882a593Smuzhiyun orr r0, r0, #PXA3_RCOMP_SWEVAL 78*4882a593Smuzhiyun str r0, [r1, #PXA3_RCOMP] 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun mov r0, #~0 @ Clear interrupts 81*4882a593Smuzhiyun str r0, [r1, #PXA3_DMCISR] 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP] 84*4882a593Smuzhiyun orr r0, r0, #PXA3_DMCIER_EDLP 85*4882a593Smuzhiyun str r0, [r1, #PXA3_DMCIER] 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN 88*4882a593Smuzhiyun bic r0, r0, #PXA3_DDR_HCAL_HCRNG 89*4882a593Smuzhiyun orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG 90*4882a593Smuzhiyun str r0, [r1, #PXA3_DDR_HCAL] 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun1: ldr r0, [r1, #PXA3_DMCISR] 93*4882a593Smuzhiyun tst r0, #PXA3_DMCIER_EDLP 94*4882a593Smuzhiyun beq 1b 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN] 97*4882a593Smuzhiyun orr r0, r0, #PXA3_MDCNFG_DMCEN 98*4882a593Smuzhiyun str r0, [r1, #PXA3_MDCNFG] 99*4882a593Smuzhiyun1: ldr r0, [r1, #PXA3_MDCNFG] 100*4882a593Smuzhiyun tst r0, #PXA3_MDCNFG_DMCEN 101*4882a593Smuzhiyun beq 1b 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG] 104*4882a593Smuzhiyun orr r0, r0, #2 @ HCRNG 105*4882a593Smuzhiyun str r0, [r1, #PXA3_DDR_HCAL] 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt 108*4882a593Smuzhiyun bic r0, r0, #0x20000000 109*4882a593Smuzhiyun str r0, [r1, #PXA3_DMCIER] 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun ret lr 112*4882a593SmuzhiyunENTRY(pm_enter_standby_end) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun#endif 115