1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_MACH_REGS_RTC_H 3*4882a593Smuzhiyun #define __ASM_MACH_REGS_RTC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <mach/hardware.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * Real Time Clock 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define RCNR __REG(0x40900000) /* RTC Count Register */ 12*4882a593Smuzhiyun #define RTAR __REG(0x40900004) /* RTC Alarm Register */ 13*4882a593Smuzhiyun #define RTSR __REG(0x40900008) /* RTC Status Register */ 14*4882a593Smuzhiyun #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ 15*4882a593Smuzhiyun #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ 18*4882a593Smuzhiyun #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ 19*4882a593Smuzhiyun #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ 20*4882a593Smuzhiyun #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ 21*4882a593Smuzhiyun #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ 22*4882a593Smuzhiyun #define RTSR_AL (1 << 0) /* RTC alarm detected */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif /* __ASM_MACH_REGS_RTC_H */ 25