xref: /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/pcm990-baseboard.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  arch/arm/mach-pxa/pcm990-baseboard.c
4*4882a593Smuzhiyun  *  Support for the Phytec phyCORE-PXA270 Development Platform (PCM-990).
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  *  Refer
7*4882a593Smuzhiyun  *   http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-XScale-PXA270.html
8*4882a593Smuzhiyun  *  for additional hardware info
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  *  Author:	Juergen Kilb
11*4882a593Smuzhiyun  *  Created:	April 05, 2005
12*4882a593Smuzhiyun  *  Copyright:	Phytec Messtechnik GmbH
13*4882a593Smuzhiyun  *  e-Mail:	armlinux@phytec.de
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  *  based on Intel Mainstone Board
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  *  Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun #include <linux/gpio.h>
20*4882a593Smuzhiyun #include <linux/irq.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun #include <linux/i2c.h>
23*4882a593Smuzhiyun #include <linux/platform_data/i2c-pxa.h>
24*4882a593Smuzhiyun #include <linux/pwm.h>
25*4882a593Smuzhiyun #include <linux/pwm_backlight.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include <asm/mach/map.h>
28*4882a593Smuzhiyun #include "pxa27x.h"
29*4882a593Smuzhiyun #include <mach/audio.h>
30*4882a593Smuzhiyun #include <linux/platform_data/mmc-pxamci.h>
31*4882a593Smuzhiyun #include <linux/platform_data/usb-ohci-pxa27x.h>
32*4882a593Smuzhiyun #include "pcm990_baseboard.h"
33*4882a593Smuzhiyun #include <linux/platform_data/video-pxafb.h>
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #include "devices.h"
36*4882a593Smuzhiyun #include "generic.h"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun static unsigned long pcm990_pin_config[] __initdata = {
39*4882a593Smuzhiyun 	/* MMC */
40*4882a593Smuzhiyun 	GPIO32_MMC_CLK,
41*4882a593Smuzhiyun 	GPIO112_MMC_CMD,
42*4882a593Smuzhiyun 	GPIO92_MMC_DAT_0,
43*4882a593Smuzhiyun 	GPIO109_MMC_DAT_1,
44*4882a593Smuzhiyun 	GPIO110_MMC_DAT_2,
45*4882a593Smuzhiyun 	GPIO111_MMC_DAT_3,
46*4882a593Smuzhiyun 	/* USB */
47*4882a593Smuzhiyun 	GPIO88_USBH1_PWR,
48*4882a593Smuzhiyun 	GPIO89_USBH1_PEN,
49*4882a593Smuzhiyun 	/* PWM0 */
50*4882a593Smuzhiyun 	GPIO16_PWM0_OUT,
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	/* I2C */
53*4882a593Smuzhiyun 	GPIO117_I2C_SCL,
54*4882a593Smuzhiyun 	GPIO118_I2C_SDA,
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	/* AC97 */
57*4882a593Smuzhiyun 	GPIO28_AC97_BITCLK,
58*4882a593Smuzhiyun 	GPIO29_AC97_SDATA_IN_0,
59*4882a593Smuzhiyun 	GPIO30_AC97_SDATA_OUT,
60*4882a593Smuzhiyun 	GPIO31_AC97_SYNC,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun static void __iomem *pcm990_cpld_base;
64*4882a593Smuzhiyun 
pcm990_cpld_readb(unsigned int reg)65*4882a593Smuzhiyun static u8 pcm990_cpld_readb(unsigned int reg)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	return readb(pcm990_cpld_base + reg);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
pcm990_cpld_writeb(u8 value,unsigned int reg)70*4882a593Smuzhiyun static void pcm990_cpld_writeb(u8 value, unsigned int reg)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	writeb(value, pcm990_cpld_base + reg);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun  * pcm990_lcd_power - control power supply to the LCD
77*4882a593Smuzhiyun  * @on: 0 = switch off, 1 = switch on
78*4882a593Smuzhiyun  *
79*4882a593Smuzhiyun  * Called by the pxafb driver
80*4882a593Smuzhiyun  */
81*4882a593Smuzhiyun #ifndef CONFIG_PCM990_DISPLAY_NONE
pcm990_lcd_power(int on,struct fb_var_screeninfo * var)82*4882a593Smuzhiyun static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	if (on) {
85*4882a593Smuzhiyun 		/* enable LCD-Latches
86*4882a593Smuzhiyun 		 * power on LCD
87*4882a593Smuzhiyun 		 */
88*4882a593Smuzhiyun 		pcm990_cpld_writeb(PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON,
89*4882a593Smuzhiyun 				PCM990_CTRL_REG3);
90*4882a593Smuzhiyun 	} else {
91*4882a593Smuzhiyun 		/* disable LCD-Latches
92*4882a593Smuzhiyun 		 * power off LCD
93*4882a593Smuzhiyun 		 */
94*4882a593Smuzhiyun 		pcm990_cpld_writeb(0, PCM990_CTRL_REG3);
95*4882a593Smuzhiyun 	}
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #if defined(CONFIG_PCM990_DISPLAY_SHARP)
100*4882a593Smuzhiyun static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
101*4882a593Smuzhiyun 	.pixclock		= 28000,
102*4882a593Smuzhiyun 	.xres			= 640,
103*4882a593Smuzhiyun 	.yres			= 480,
104*4882a593Smuzhiyun 	.bpp			= 16,
105*4882a593Smuzhiyun 	.hsync_len		= 20,
106*4882a593Smuzhiyun 	.left_margin		= 103,
107*4882a593Smuzhiyun 	.right_margin		= 47,
108*4882a593Smuzhiyun 	.vsync_len		= 6,
109*4882a593Smuzhiyun 	.upper_margin		= 28,
110*4882a593Smuzhiyun 	.lower_margin		= 5,
111*4882a593Smuzhiyun 	.sync			= 0,
112*4882a593Smuzhiyun 	.cmap_greyscale		= 0,
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static struct pxafb_mach_info pcm990_fbinfo __initdata = {
116*4882a593Smuzhiyun 	.modes			= &fb_info_sharp_lq084v1dg21,
117*4882a593Smuzhiyun 	.num_modes		= 1,
118*4882a593Smuzhiyun 	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
119*4882a593Smuzhiyun 	.pxafb_lcd_power	= pcm990_lcd_power,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun #elif defined(CONFIG_PCM990_DISPLAY_NEC)
122*4882a593Smuzhiyun struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
123*4882a593Smuzhiyun 	.pixclock		= 39720,
124*4882a593Smuzhiyun 	.xres			= 640,
125*4882a593Smuzhiyun 	.yres			= 480,
126*4882a593Smuzhiyun 	.bpp			= 16,
127*4882a593Smuzhiyun 	.hsync_len		= 32,
128*4882a593Smuzhiyun 	.left_margin		= 16,
129*4882a593Smuzhiyun 	.right_margin		= 48,
130*4882a593Smuzhiyun 	.vsync_len		= 2,
131*4882a593Smuzhiyun 	.upper_margin		= 12,
132*4882a593Smuzhiyun 	.lower_margin		= 17,
133*4882a593Smuzhiyun 	.sync			= 0,
134*4882a593Smuzhiyun 	.cmap_greyscale		= 0,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static struct pxafb_mach_info pcm990_fbinfo __initdata = {
138*4882a593Smuzhiyun 	.modes			= &fb_info_nec_nl6448bc20_18d,
139*4882a593Smuzhiyun 	.num_modes		= 1,
140*4882a593Smuzhiyun 	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
141*4882a593Smuzhiyun 	.pxafb_lcd_power	= pcm990_lcd_power,
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun #endif
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun static struct pwm_lookup pcm990_pwm_lookup[] = {
146*4882a593Smuzhiyun 	PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
147*4882a593Smuzhiyun 		   PWM_POLARITY_NORMAL),
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun static struct platform_pwm_backlight_data pcm990_backlight_data = {
151*4882a593Smuzhiyun 	.max_brightness	= 1023,
152*4882a593Smuzhiyun 	.dft_brightness	= 1023,
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun static struct platform_device pcm990_backlight_device = {
156*4882a593Smuzhiyun 	.name		= "pwm-backlight",
157*4882a593Smuzhiyun 	.dev		= {
158*4882a593Smuzhiyun 		.parent = &pxa27x_device_pwm0.dev,
159*4882a593Smuzhiyun 		.platform_data = &pcm990_backlight_data,
160*4882a593Smuzhiyun 	},
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun /*
164*4882a593Smuzhiyun  * The PCM-990 development baseboard uses PCM-027's hardware in the
165*4882a593Smuzhiyun  * following way:
166*4882a593Smuzhiyun  *
167*4882a593Smuzhiyun  * - LCD support is in use
168*4882a593Smuzhiyun  *  - GPIO16 is output for back light on/off with PWM
169*4882a593Smuzhiyun  *  - GPIO58 ... GPIO73 are outputs for display data
170*4882a593Smuzhiyun  *  - GPIO74 is output output for LCDFCLK
171*4882a593Smuzhiyun  *  - GPIO75 is output for LCDLCLK
172*4882a593Smuzhiyun  *  - GPIO76 is output for LCDPCLK
173*4882a593Smuzhiyun  *  - GPIO77 is output for LCDBIAS
174*4882a593Smuzhiyun  * - MMC support is in use
175*4882a593Smuzhiyun  *  - GPIO32 is output for MMCCLK
176*4882a593Smuzhiyun  *  - GPIO92 is MMDAT0
177*4882a593Smuzhiyun  *  - GPIO109 is MMDAT1
178*4882a593Smuzhiyun  *  - GPIO110 is MMCS0
179*4882a593Smuzhiyun  *  - GPIO111 is MMCS1
180*4882a593Smuzhiyun  *  - GPIO112 is MMCMD
181*4882a593Smuzhiyun  * - IDE/CF card is in use
182*4882a593Smuzhiyun  *  - GPIO48 is output /POE
183*4882a593Smuzhiyun  *  - GPIO49 is output /PWE
184*4882a593Smuzhiyun  *  - GPIO50 is output /PIOR
185*4882a593Smuzhiyun  *  - GPIO51 is output /PIOW
186*4882a593Smuzhiyun  *  - GPIO54 is output /PCE2
187*4882a593Smuzhiyun  *  - GPIO55 is output /PREG
188*4882a593Smuzhiyun  *  - GPIO56 is input /PWAIT
189*4882a593Smuzhiyun  *  - GPIO57 is output /PIOS16
190*4882a593Smuzhiyun  *  - GPIO79 is output PSKTSEL
191*4882a593Smuzhiyun  *  - GPIO85 is output /PCE1
192*4882a593Smuzhiyun  * - FFUART is in use
193*4882a593Smuzhiyun  *  - GPIO34 is input FFRXD
194*4882a593Smuzhiyun  *  - GPIO35 is input FFCTS
195*4882a593Smuzhiyun  *  - GPIO36 is input FFDCD
196*4882a593Smuzhiyun  *  - GPIO37 is input FFDSR
197*4882a593Smuzhiyun  *  - GPIO38 is input FFRI
198*4882a593Smuzhiyun  *  - GPIO39 is output FFTXD
199*4882a593Smuzhiyun  *  - GPIO40 is output FFDTR
200*4882a593Smuzhiyun  *  - GPIO41 is output FFRTS
201*4882a593Smuzhiyun  * - BTUART is in use
202*4882a593Smuzhiyun  *  - GPIO42 is input BTRXD
203*4882a593Smuzhiyun  *  - GPIO43 is output BTTXD
204*4882a593Smuzhiyun  *  - GPIO44 is input BTCTS
205*4882a593Smuzhiyun  *  - GPIO45 is output BTRTS
206*4882a593Smuzhiyun  * - IRUART is in use
207*4882a593Smuzhiyun  *  - GPIO46 is input STDRXD
208*4882a593Smuzhiyun  *  - GPIO47 is output STDTXD
209*4882a593Smuzhiyun  * - AC97 is in use*)
210*4882a593Smuzhiyun  *  - GPIO28 is input AC97CLK
211*4882a593Smuzhiyun  *  - GPIO29 is input AC97DatIn
212*4882a593Smuzhiyun  *  - GPIO30 is output AC97DatO
213*4882a593Smuzhiyun  *  - GPIO31 is output AC97SYNC
214*4882a593Smuzhiyun  *  - GPIO113 is output AC97_RESET
215*4882a593Smuzhiyun  * - SSP is in use
216*4882a593Smuzhiyun  *  - GPIO23 is output SSPSCLK
217*4882a593Smuzhiyun  *  - GPIO24 is output chip select to Max7301
218*4882a593Smuzhiyun  *  - GPIO25 is output SSPTXD
219*4882a593Smuzhiyun  *  - GPIO26 is input SSPRXD
220*4882a593Smuzhiyun  *  - GPIO27 is input for Max7301 IRQ
221*4882a593Smuzhiyun  *  - GPIO53 is input SSPSYSCLK
222*4882a593Smuzhiyun  * - SSP3 is in use
223*4882a593Smuzhiyun  *  - GPIO81 is output SSPTXD3
224*4882a593Smuzhiyun  *  - GPIO82 is input SSPRXD3
225*4882a593Smuzhiyun  *  - GPIO83 is output SSPSFRM
226*4882a593Smuzhiyun  *  - GPIO84 is output SSPCLK3
227*4882a593Smuzhiyun  *
228*4882a593Smuzhiyun  * Otherwise claimed GPIOs:
229*4882a593Smuzhiyun  * GPIO1 -> IRQ from user switch
230*4882a593Smuzhiyun  * GPIO9 -> IRQ from power management
231*4882a593Smuzhiyun  * GPIO10 -> IRQ from WML9712 AC97 controller
232*4882a593Smuzhiyun  * GPIO11 -> IRQ from IDE controller
233*4882a593Smuzhiyun  * GPIO12 -> IRQ from CF controller
234*4882a593Smuzhiyun  * GPIO13 -> IRQ from CF controller
235*4882a593Smuzhiyun  * GPIO14 -> GPIO free
236*4882a593Smuzhiyun  * GPIO15 -> /CS1 selects baseboard's Control CPLD (U7, 16 bit wide data path)
237*4882a593Smuzhiyun  * GPIO19 -> GPIO free
238*4882a593Smuzhiyun  * GPIO20 -> /SDCS2
239*4882a593Smuzhiyun  * GPIO21 -> /CS3 PC card socket select
240*4882a593Smuzhiyun  * GPIO33 -> /CS5  network controller select
241*4882a593Smuzhiyun  * GPIO78 -> /CS2  (16 bit wide data path)
242*4882a593Smuzhiyun  * GPIO80 -> /CS4  (16 bit wide data path)
243*4882a593Smuzhiyun  * GPIO86 -> GPIO free
244*4882a593Smuzhiyun  * GPIO87 -> GPIO free
245*4882a593Smuzhiyun  * GPIO90 -> LED0 on CPU module
246*4882a593Smuzhiyun  * GPIO91 -> LED1 on CPI module
247*4882a593Smuzhiyun  * GPIO117 -> SCL
248*4882a593Smuzhiyun  * GPIO118 -> SDA
249*4882a593Smuzhiyun  */
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun static unsigned long pcm990_irq_enabled;
252*4882a593Smuzhiyun 
pcm990_mask_ack_irq(struct irq_data * d)253*4882a593Smuzhiyun static void pcm990_mask_ack_irq(struct irq_data *d)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun 	int pcm990_irq = (d->irq - PCM027_IRQ(0));
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	pcm990_irq_enabled &= ~(1 << pcm990_irq);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
pcm990_unmask_irq(struct irq_data * d)262*4882a593Smuzhiyun static void pcm990_unmask_irq(struct irq_data *d)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun 	int pcm990_irq = (d->irq - PCM027_IRQ(0));
265*4882a593Smuzhiyun 	u8 val;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	/* the irq can be acknowledged only if deasserted, so it's done here */
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	pcm990_irq_enabled |= (1 << pcm990_irq);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	val = pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
272*4882a593Smuzhiyun 	val |= 1 << pcm990_irq;
273*4882a593Smuzhiyun 	pcm990_cpld_writeb(val, PCM990_CTRL_INTSETCLR);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun static struct irq_chip pcm990_irq_chip = {
279*4882a593Smuzhiyun 	.irq_mask_ack	= pcm990_mask_ack_irq,
280*4882a593Smuzhiyun 	.irq_unmask	= pcm990_unmask_irq,
281*4882a593Smuzhiyun };
282*4882a593Smuzhiyun 
pcm990_irq_handler(struct irq_desc * desc)283*4882a593Smuzhiyun static void pcm990_irq_handler(struct irq_desc *desc)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	unsigned int irq;
286*4882a593Smuzhiyun 	unsigned long pending;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
289*4882a593Smuzhiyun 	pending &= pcm990_irq_enabled;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	do {
292*4882a593Smuzhiyun 		/* clear our parent IRQ */
293*4882a593Smuzhiyun 		desc->irq_data.chip->irq_ack(&desc->irq_data);
294*4882a593Smuzhiyun 		if (likely(pending)) {
295*4882a593Smuzhiyun 			irq = PCM027_IRQ(0) + __ffs(pending);
296*4882a593Smuzhiyun 			generic_handle_irq(irq);
297*4882a593Smuzhiyun 		}
298*4882a593Smuzhiyun 		pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
299*4882a593Smuzhiyun 		pending &= pcm990_irq_enabled;
300*4882a593Smuzhiyun 	} while (pending);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
pcm990_init_irq(void)303*4882a593Smuzhiyun static void __init pcm990_init_irq(void)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun 	int irq;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	/* setup extra PCM990 irqs */
308*4882a593Smuzhiyun 	for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
309*4882a593Smuzhiyun 		irq_set_chip_and_handler(irq, &pcm990_irq_chip,
310*4882a593Smuzhiyun 					 handle_level_irq);
311*4882a593Smuzhiyun 		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
312*4882a593Smuzhiyun 	}
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	/* disable all Interrupts */
315*4882a593Smuzhiyun 	pcm990_cpld_writeb(0x0, PCM990_CTRL_INTMSKENA);
316*4882a593Smuzhiyun 	pcm990_cpld_writeb(0xff, PCM990_CTRL_INTSETCLR);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
319*4882a593Smuzhiyun 	irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun 
pcm990_mci_init(struct device * dev,irq_handler_t mci_detect_int,void * data)322*4882a593Smuzhiyun static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
323*4882a593Smuzhiyun 			void *data)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun 	int err;
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, 0,
328*4882a593Smuzhiyun 			     "MMC card detect", data);
329*4882a593Smuzhiyun 	if (err)
330*4882a593Smuzhiyun 		printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC "
331*4882a593Smuzhiyun 				"card detect IRQ\n");
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	return err;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun 
pcm990_mci_setpower(struct device * dev,unsigned int vdd)336*4882a593Smuzhiyun static int pcm990_mci_setpower(struct device *dev, unsigned int vdd)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun 	struct pxamci_platform_data *p_d = dev->platform_data;
339*4882a593Smuzhiyun 	u8 val;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	val = pcm990_cpld_readb(PCM990_CTRL_REG5);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	if ((1 << vdd) & p_d->ocr_mask)
344*4882a593Smuzhiyun 		val |= PCM990_CTRL_MMC2PWR;
345*4882a593Smuzhiyun 	else
346*4882a593Smuzhiyun 		val &= ~PCM990_CTRL_MMC2PWR;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
349*4882a593Smuzhiyun 	return 0;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun 
pcm990_mci_exit(struct device * dev,void * data)352*4882a593Smuzhiyun static void pcm990_mci_exit(struct device *dev, void *data)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun 	free_irq(PCM027_MMCDET_IRQ, data);
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun #define MSECS_PER_JIFFY (1000/HZ)
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun static struct pxamci_platform_data pcm990_mci_platform_data = {
360*4882a593Smuzhiyun 	.detect_delay_ms	= 250,
361*4882a593Smuzhiyun 	.ocr_mask		= MMC_VDD_32_33 | MMC_VDD_33_34,
362*4882a593Smuzhiyun 	.init 			= pcm990_mci_init,
363*4882a593Smuzhiyun 	.setpower 		= pcm990_mci_setpower,
364*4882a593Smuzhiyun 	.exit			= pcm990_mci_exit,
365*4882a593Smuzhiyun };
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun static struct pxaohci_platform_data pcm990_ohci_platform_data = {
368*4882a593Smuzhiyun 	.port_mode	= PMM_PERPORT_MODE,
369*4882a593Smuzhiyun 	.flags		= ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
370*4882a593Smuzhiyun 	.power_on_delay	= 10,
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun /*
374*4882a593Smuzhiyun  * system init for baseboard usage. Will be called by pcm027 init.
375*4882a593Smuzhiyun  *
376*4882a593Smuzhiyun  * Add platform devices present on this baseboard and init
377*4882a593Smuzhiyun  * them from CPU side as far as required to use them later on
378*4882a593Smuzhiyun  */
pcm990_baseboard_init(void)379*4882a593Smuzhiyun void __init pcm990_baseboard_init(void)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_pin_config));
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	pcm990_cpld_base = ioremap(PCM990_CTRL_PHYS, PCM990_CTRL_SIZE);
384*4882a593Smuzhiyun 	if (!pcm990_cpld_base) {
385*4882a593Smuzhiyun 		pr_err("pcm990: failed to ioremap cpld\n");
386*4882a593Smuzhiyun 		return;
387*4882a593Smuzhiyun 	}
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	/* register CPLD's IRQ controller */
390*4882a593Smuzhiyun 	pcm990_init_irq();
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun #ifndef CONFIG_PCM990_DISPLAY_NONE
393*4882a593Smuzhiyun 	pxa_set_fb_info(NULL, &pcm990_fbinfo);
394*4882a593Smuzhiyun #endif
395*4882a593Smuzhiyun 	pwm_add_table(pcm990_pwm_lookup, ARRAY_SIZE(pcm990_pwm_lookup));
396*4882a593Smuzhiyun 	platform_device_register(&pcm990_backlight_device);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	/* MMC */
399*4882a593Smuzhiyun 	pxa_set_mci_info(&pcm990_mci_platform_data);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	/* USB host */
402*4882a593Smuzhiyun 	pxa_set_ohci_info(&pcm990_ohci_platform_data);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	pxa_set_i2c_info(NULL);
405*4882a593Smuzhiyun 	pxa_set_ac97_info(NULL);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	printk(KERN_INFO "PCM-990 Evaluation baseboard initialized\n");
408*4882a593Smuzhiyun }
409