1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/arm/mach-pxa/lpd270.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Support for the LogicPD PXA270 Card Engine.
6*4882a593Smuzhiyun * Derived from the mainstone code, which carries these notices:
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Nicolas Pitre
9*4882a593Smuzhiyun * Created: Nov 05, 2002
10*4882a593Smuzhiyun * Copyright: MontaVista Software Inc.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <linux/gpio.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/syscore_ops.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/sched.h>
18*4882a593Smuzhiyun #include <linux/bitops.h>
19*4882a593Smuzhiyun #include <linux/fb.h>
20*4882a593Smuzhiyun #include <linux/ioport.h>
21*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
22*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
23*4882a593Smuzhiyun #include <linux/pwm.h>
24*4882a593Smuzhiyun #include <linux/pwm_backlight.h>
25*4882a593Smuzhiyun #include <linux/smc91x.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <asm/types.h>
28*4882a593Smuzhiyun #include <asm/setup.h>
29*4882a593Smuzhiyun #include <asm/memory.h>
30*4882a593Smuzhiyun #include <asm/mach-types.h>
31*4882a593Smuzhiyun #include <mach/hardware.h>
32*4882a593Smuzhiyun #include <asm/irq.h>
33*4882a593Smuzhiyun #include <linux/sizes.h>
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include <asm/mach/arch.h>
36*4882a593Smuzhiyun #include <asm/mach/map.h>
37*4882a593Smuzhiyun #include <asm/mach/irq.h>
38*4882a593Smuzhiyun #include <asm/mach/flash.h>
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #include "pxa27x.h"
41*4882a593Smuzhiyun #include "lpd270.h"
42*4882a593Smuzhiyun #include <mach/audio.h>
43*4882a593Smuzhiyun #include <linux/platform_data/video-pxafb.h>
44*4882a593Smuzhiyun #include <linux/platform_data/mmc-pxamci.h>
45*4882a593Smuzhiyun #include <linux/platform_data/irda-pxaficp.h>
46*4882a593Smuzhiyun #include <linux/platform_data/usb-ohci-pxa27x.h>
47*4882a593Smuzhiyun #include <mach/smemc.h>
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include "generic.h"
50*4882a593Smuzhiyun #include "devices.h"
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static unsigned long lpd270_pin_config[] __initdata = {
53*4882a593Smuzhiyun /* Chip Selects */
54*4882a593Smuzhiyun GPIO15_nCS_1, /* Mainboard Flash */
55*4882a593Smuzhiyun GPIO78_nCS_2, /* CPLD + Ethernet */
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* LCD - 16bpp Active TFT */
58*4882a593Smuzhiyun GPIO58_LCD_LDD_0,
59*4882a593Smuzhiyun GPIO59_LCD_LDD_1,
60*4882a593Smuzhiyun GPIO60_LCD_LDD_2,
61*4882a593Smuzhiyun GPIO61_LCD_LDD_3,
62*4882a593Smuzhiyun GPIO62_LCD_LDD_4,
63*4882a593Smuzhiyun GPIO63_LCD_LDD_5,
64*4882a593Smuzhiyun GPIO64_LCD_LDD_6,
65*4882a593Smuzhiyun GPIO65_LCD_LDD_7,
66*4882a593Smuzhiyun GPIO66_LCD_LDD_8,
67*4882a593Smuzhiyun GPIO67_LCD_LDD_9,
68*4882a593Smuzhiyun GPIO68_LCD_LDD_10,
69*4882a593Smuzhiyun GPIO69_LCD_LDD_11,
70*4882a593Smuzhiyun GPIO70_LCD_LDD_12,
71*4882a593Smuzhiyun GPIO71_LCD_LDD_13,
72*4882a593Smuzhiyun GPIO72_LCD_LDD_14,
73*4882a593Smuzhiyun GPIO73_LCD_LDD_15,
74*4882a593Smuzhiyun GPIO74_LCD_FCLK,
75*4882a593Smuzhiyun GPIO75_LCD_LCLK,
76*4882a593Smuzhiyun GPIO76_LCD_PCLK,
77*4882a593Smuzhiyun GPIO77_LCD_BIAS,
78*4882a593Smuzhiyun GPIO16_PWM0_OUT, /* Backlight */
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* USB Host */
81*4882a593Smuzhiyun GPIO88_USBH1_PWR,
82*4882a593Smuzhiyun GPIO89_USBH1_PEN,
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* AC97 */
85*4882a593Smuzhiyun GPIO28_AC97_BITCLK,
86*4882a593Smuzhiyun GPIO29_AC97_SDATA_IN_0,
87*4882a593Smuzhiyun GPIO30_AC97_SDATA_OUT,
88*4882a593Smuzhiyun GPIO31_AC97_SYNC,
89*4882a593Smuzhiyun GPIO45_AC97_SYSCLK,
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static unsigned int lpd270_irq_enabled;
95*4882a593Smuzhiyun
lpd270_mask_irq(struct irq_data * d)96*4882a593Smuzhiyun static void lpd270_mask_irq(struct irq_data *d)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun int lpd270_irq = d->irq - LPD270_IRQ(0);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun lpd270_irq_enabled &= ~(1 << lpd270_irq);
103*4882a593Smuzhiyun __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
lpd270_unmask_irq(struct irq_data * d)106*4882a593Smuzhiyun static void lpd270_unmask_irq(struct irq_data *d)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun int lpd270_irq = d->irq - LPD270_IRQ(0);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun lpd270_irq_enabled |= 1 << lpd270_irq;
111*4882a593Smuzhiyun __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static struct irq_chip lpd270_irq_chip = {
115*4882a593Smuzhiyun .name = "CPLD",
116*4882a593Smuzhiyun .irq_ack = lpd270_mask_irq,
117*4882a593Smuzhiyun .irq_mask = lpd270_mask_irq,
118*4882a593Smuzhiyun .irq_unmask = lpd270_unmask_irq,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
lpd270_irq_handler(struct irq_desc * desc)121*4882a593Smuzhiyun static void lpd270_irq_handler(struct irq_desc *desc)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun unsigned int irq;
124*4882a593Smuzhiyun unsigned long pending;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
127*4882a593Smuzhiyun do {
128*4882a593Smuzhiyun /* clear useless edge notification */
129*4882a593Smuzhiyun desc->irq_data.chip->irq_ack(&desc->irq_data);
130*4882a593Smuzhiyun if (likely(pending)) {
131*4882a593Smuzhiyun irq = LPD270_IRQ(0) + __ffs(pending);
132*4882a593Smuzhiyun generic_handle_irq(irq);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun pending = __raw_readw(LPD270_INT_STATUS) &
135*4882a593Smuzhiyun lpd270_irq_enabled;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun } while (pending);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
lpd270_init_irq(void)140*4882a593Smuzhiyun static void __init lpd270_init_irq(void)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun int irq;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun pxa27x_init_irq();
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun __raw_writew(0, LPD270_INT_MASK);
147*4882a593Smuzhiyun __raw_writew(0, LPD270_INT_STATUS);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* setup extra LogicPD PXA270 irqs */
150*4882a593Smuzhiyun for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
151*4882a593Smuzhiyun irq_set_chip_and_handler(irq, &lpd270_irq_chip,
152*4882a593Smuzhiyun handle_level_irq);
153*4882a593Smuzhiyun irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
156*4882a593Smuzhiyun irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #ifdef CONFIG_PM
lpd270_irq_resume(void)161*4882a593Smuzhiyun static void lpd270_irq_resume(void)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun static struct syscore_ops lpd270_irq_syscore_ops = {
167*4882a593Smuzhiyun .resume = lpd270_irq_resume,
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
lpd270_irq_device_init(void)170*4882a593Smuzhiyun static int __init lpd270_irq_device_init(void)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun if (machine_is_logicpd_pxa270()) {
173*4882a593Smuzhiyun register_syscore_ops(&lpd270_irq_syscore_ops);
174*4882a593Smuzhiyun return 0;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun return -ENODEV;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun device_initcall(lpd270_irq_device_init);
180*4882a593Smuzhiyun #endif
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static struct resource smc91x_resources[] = {
184*4882a593Smuzhiyun [0] = {
185*4882a593Smuzhiyun .start = LPD270_ETH_PHYS,
186*4882a593Smuzhiyun .end = (LPD270_ETH_PHYS + 0xfffff),
187*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
188*4882a593Smuzhiyun },
189*4882a593Smuzhiyun [1] = {
190*4882a593Smuzhiyun .start = LPD270_ETHERNET_IRQ,
191*4882a593Smuzhiyun .end = LPD270_ETHERNET_IRQ,
192*4882a593Smuzhiyun .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
193*4882a593Smuzhiyun },
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun struct smc91x_platdata smc91x_platdata = {
197*4882a593Smuzhiyun .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static struct platform_device smc91x_device = {
201*4882a593Smuzhiyun .name = "smc91x",
202*4882a593Smuzhiyun .id = 0,
203*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(smc91x_resources),
204*4882a593Smuzhiyun .resource = smc91x_resources,
205*4882a593Smuzhiyun .dev.platform_data = &smc91x_platdata,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun static struct resource lpd270_flash_resources[] = {
209*4882a593Smuzhiyun [0] = {
210*4882a593Smuzhiyun .start = PXA_CS0_PHYS,
211*4882a593Smuzhiyun .end = PXA_CS0_PHYS + SZ_64M - 1,
212*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
213*4882a593Smuzhiyun },
214*4882a593Smuzhiyun [1] = {
215*4882a593Smuzhiyun .start = PXA_CS1_PHYS,
216*4882a593Smuzhiyun .end = PXA_CS1_PHYS + SZ_64M - 1,
217*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
218*4882a593Smuzhiyun },
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun static struct mtd_partition lpd270_flash0_partitions[] = {
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun .name = "Bootloader",
224*4882a593Smuzhiyun .size = 0x00040000,
225*4882a593Smuzhiyun .offset = 0,
226*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE /* force read-only */
227*4882a593Smuzhiyun }, {
228*4882a593Smuzhiyun .name = "Kernel",
229*4882a593Smuzhiyun .size = 0x00400000,
230*4882a593Smuzhiyun .offset = 0x00040000,
231*4882a593Smuzhiyun }, {
232*4882a593Smuzhiyun .name = "Filesystem",
233*4882a593Smuzhiyun .size = MTDPART_SIZ_FULL,
234*4882a593Smuzhiyun .offset = 0x00440000
235*4882a593Smuzhiyun },
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun static struct flash_platform_data lpd270_flash_data[2] = {
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun .name = "processor-flash",
241*4882a593Smuzhiyun .map_name = "cfi_probe",
242*4882a593Smuzhiyun .parts = lpd270_flash0_partitions,
243*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
244*4882a593Smuzhiyun }, {
245*4882a593Smuzhiyun .name = "mainboard-flash",
246*4882a593Smuzhiyun .map_name = "cfi_probe",
247*4882a593Smuzhiyun .parts = NULL,
248*4882a593Smuzhiyun .nr_parts = 0,
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static struct platform_device lpd270_flash_device[2] = {
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun .name = "pxa2xx-flash",
255*4882a593Smuzhiyun .id = 0,
256*4882a593Smuzhiyun .dev = {
257*4882a593Smuzhiyun .platform_data = &lpd270_flash_data[0],
258*4882a593Smuzhiyun },
259*4882a593Smuzhiyun .resource = &lpd270_flash_resources[0],
260*4882a593Smuzhiyun .num_resources = 1,
261*4882a593Smuzhiyun }, {
262*4882a593Smuzhiyun .name = "pxa2xx-flash",
263*4882a593Smuzhiyun .id = 1,
264*4882a593Smuzhiyun .dev = {
265*4882a593Smuzhiyun .platform_data = &lpd270_flash_data[1],
266*4882a593Smuzhiyun },
267*4882a593Smuzhiyun .resource = &lpd270_flash_resources[1],
268*4882a593Smuzhiyun .num_resources = 1,
269*4882a593Smuzhiyun },
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun static struct pwm_lookup lpd270_pwm_lookup[] = {
273*4882a593Smuzhiyun PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
274*4882a593Smuzhiyun PWM_POLARITY_NORMAL),
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun static struct platform_pwm_backlight_data lpd270_backlight_data = {
278*4882a593Smuzhiyun .max_brightness = 1,
279*4882a593Smuzhiyun .dft_brightness = 1,
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun static struct platform_device lpd270_backlight_device = {
283*4882a593Smuzhiyun .name = "pwm-backlight",
284*4882a593Smuzhiyun .dev = {
285*4882a593Smuzhiyun .parent = &pxa27x_device_pwm0.dev,
286*4882a593Smuzhiyun .platform_data = &lpd270_backlight_data,
287*4882a593Smuzhiyun },
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun /* 5.7" TFT QVGA (LoLo display number 1) */
291*4882a593Smuzhiyun static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
292*4882a593Smuzhiyun .pixclock = 150000,
293*4882a593Smuzhiyun .xres = 320,
294*4882a593Smuzhiyun .yres = 240,
295*4882a593Smuzhiyun .bpp = 16,
296*4882a593Smuzhiyun .hsync_len = 0x14,
297*4882a593Smuzhiyun .left_margin = 0x28,
298*4882a593Smuzhiyun .right_margin = 0x0a,
299*4882a593Smuzhiyun .vsync_len = 0x02,
300*4882a593Smuzhiyun .upper_margin = 0x08,
301*4882a593Smuzhiyun .lower_margin = 0x14,
302*4882a593Smuzhiyun .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun static struct pxafb_mach_info sharp_lq057q3dc02 = {
306*4882a593Smuzhiyun .modes = &sharp_lq057q3dc02_mode,
307*4882a593Smuzhiyun .num_modes = 1,
308*4882a593Smuzhiyun .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
309*4882a593Smuzhiyun LCD_ALTERNATE_MAPPING,
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /* 12.1" TFT SVGA (LoLo display number 2) */
313*4882a593Smuzhiyun static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
314*4882a593Smuzhiyun .pixclock = 50000,
315*4882a593Smuzhiyun .xres = 800,
316*4882a593Smuzhiyun .yres = 600,
317*4882a593Smuzhiyun .bpp = 16,
318*4882a593Smuzhiyun .hsync_len = 0x05,
319*4882a593Smuzhiyun .left_margin = 0x52,
320*4882a593Smuzhiyun .right_margin = 0x05,
321*4882a593Smuzhiyun .vsync_len = 0x04,
322*4882a593Smuzhiyun .upper_margin = 0x14,
323*4882a593Smuzhiyun .lower_margin = 0x0a,
324*4882a593Smuzhiyun .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun static struct pxafb_mach_info sharp_lq121s1dg31 = {
328*4882a593Smuzhiyun .modes = &sharp_lq121s1dg31_mode,
329*4882a593Smuzhiyun .num_modes = 1,
330*4882a593Smuzhiyun .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
331*4882a593Smuzhiyun LCD_ALTERNATE_MAPPING,
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* 3.6" TFT QVGA (LoLo display number 3) */
335*4882a593Smuzhiyun static struct pxafb_mode_info sharp_lq036q1da01_mode = {
336*4882a593Smuzhiyun .pixclock = 150000,
337*4882a593Smuzhiyun .xres = 320,
338*4882a593Smuzhiyun .yres = 240,
339*4882a593Smuzhiyun .bpp = 16,
340*4882a593Smuzhiyun .hsync_len = 0x0e,
341*4882a593Smuzhiyun .left_margin = 0x04,
342*4882a593Smuzhiyun .right_margin = 0x0a,
343*4882a593Smuzhiyun .vsync_len = 0x03,
344*4882a593Smuzhiyun .upper_margin = 0x03,
345*4882a593Smuzhiyun .lower_margin = 0x03,
346*4882a593Smuzhiyun .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun static struct pxafb_mach_info sharp_lq036q1da01 = {
350*4882a593Smuzhiyun .modes = &sharp_lq036q1da01_mode,
351*4882a593Smuzhiyun .num_modes = 1,
352*4882a593Smuzhiyun .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
353*4882a593Smuzhiyun LCD_ALTERNATE_MAPPING,
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /* 6.4" TFT VGA (LoLo display number 5) */
357*4882a593Smuzhiyun static struct pxafb_mode_info sharp_lq64d343_mode = {
358*4882a593Smuzhiyun .pixclock = 25000,
359*4882a593Smuzhiyun .xres = 640,
360*4882a593Smuzhiyun .yres = 480,
361*4882a593Smuzhiyun .bpp = 16,
362*4882a593Smuzhiyun .hsync_len = 0x31,
363*4882a593Smuzhiyun .left_margin = 0x89,
364*4882a593Smuzhiyun .right_margin = 0x19,
365*4882a593Smuzhiyun .vsync_len = 0x12,
366*4882a593Smuzhiyun .upper_margin = 0x22,
367*4882a593Smuzhiyun .lower_margin = 0x00,
368*4882a593Smuzhiyun .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
369*4882a593Smuzhiyun };
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun static struct pxafb_mach_info sharp_lq64d343 = {
372*4882a593Smuzhiyun .modes = &sharp_lq64d343_mode,
373*4882a593Smuzhiyun .num_modes = 1,
374*4882a593Smuzhiyun .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
375*4882a593Smuzhiyun LCD_ALTERNATE_MAPPING,
376*4882a593Smuzhiyun };
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* 10.4" TFT VGA (LoLo display number 7) */
379*4882a593Smuzhiyun static struct pxafb_mode_info sharp_lq10d368_mode = {
380*4882a593Smuzhiyun .pixclock = 25000,
381*4882a593Smuzhiyun .xres = 640,
382*4882a593Smuzhiyun .yres = 480,
383*4882a593Smuzhiyun .bpp = 16,
384*4882a593Smuzhiyun .hsync_len = 0x31,
385*4882a593Smuzhiyun .left_margin = 0x89,
386*4882a593Smuzhiyun .right_margin = 0x19,
387*4882a593Smuzhiyun .vsync_len = 0x12,
388*4882a593Smuzhiyun .upper_margin = 0x22,
389*4882a593Smuzhiyun .lower_margin = 0x00,
390*4882a593Smuzhiyun .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun static struct pxafb_mach_info sharp_lq10d368 = {
394*4882a593Smuzhiyun .modes = &sharp_lq10d368_mode,
395*4882a593Smuzhiyun .num_modes = 1,
396*4882a593Smuzhiyun .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
397*4882a593Smuzhiyun LCD_ALTERNATE_MAPPING,
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun /* 3.5" TFT QVGA (LoLo display number 8) */
401*4882a593Smuzhiyun static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
402*4882a593Smuzhiyun .pixclock = 150000,
403*4882a593Smuzhiyun .xres = 240,
404*4882a593Smuzhiyun .yres = 320,
405*4882a593Smuzhiyun .bpp = 16,
406*4882a593Smuzhiyun .hsync_len = 0x0e,
407*4882a593Smuzhiyun .left_margin = 0x0a,
408*4882a593Smuzhiyun .right_margin = 0x0a,
409*4882a593Smuzhiyun .vsync_len = 0x03,
410*4882a593Smuzhiyun .upper_margin = 0x05,
411*4882a593Smuzhiyun .lower_margin = 0x14,
412*4882a593Smuzhiyun .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
413*4882a593Smuzhiyun };
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun static struct pxafb_mach_info sharp_lq035q7db02_20 = {
416*4882a593Smuzhiyun .modes = &sharp_lq035q7db02_20_mode,
417*4882a593Smuzhiyun .num_modes = 1,
418*4882a593Smuzhiyun .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
419*4882a593Smuzhiyun LCD_ALTERNATE_MAPPING,
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun static struct pxafb_mach_info *lpd270_lcd_to_use;
423*4882a593Smuzhiyun
lpd270_set_lcd(char * str)424*4882a593Smuzhiyun static int __init lpd270_set_lcd(char *str)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun if (!strncasecmp(str, "lq057q3dc02", 11)) {
427*4882a593Smuzhiyun lpd270_lcd_to_use = &sharp_lq057q3dc02;
428*4882a593Smuzhiyun } else if (!strncasecmp(str, "lq121s1dg31", 11)) {
429*4882a593Smuzhiyun lpd270_lcd_to_use = &sharp_lq121s1dg31;
430*4882a593Smuzhiyun } else if (!strncasecmp(str, "lq036q1da01", 11)) {
431*4882a593Smuzhiyun lpd270_lcd_to_use = &sharp_lq036q1da01;
432*4882a593Smuzhiyun } else if (!strncasecmp(str, "lq64d343", 8)) {
433*4882a593Smuzhiyun lpd270_lcd_to_use = &sharp_lq64d343;
434*4882a593Smuzhiyun } else if (!strncasecmp(str, "lq10d368", 8)) {
435*4882a593Smuzhiyun lpd270_lcd_to_use = &sharp_lq10d368;
436*4882a593Smuzhiyun } else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
437*4882a593Smuzhiyun lpd270_lcd_to_use = &sharp_lq035q7db02_20;
438*4882a593Smuzhiyun } else {
439*4882a593Smuzhiyun printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun return 1;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun __setup("lcd=", lpd270_set_lcd);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun static struct platform_device *platform_devices[] __initdata = {
448*4882a593Smuzhiyun &smc91x_device,
449*4882a593Smuzhiyun &lpd270_backlight_device,
450*4882a593Smuzhiyun &lpd270_flash_device[0],
451*4882a593Smuzhiyun &lpd270_flash_device[1],
452*4882a593Smuzhiyun };
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun static struct pxaohci_platform_data lpd270_ohci_platform_data = {
455*4882a593Smuzhiyun .port_mode = PMM_PERPORT_MODE,
456*4882a593Smuzhiyun .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun
lpd270_init(void)459*4882a593Smuzhiyun static void __init lpd270_init(void)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun pxa_set_ffuart_info(NULL);
464*4882a593Smuzhiyun pxa_set_btuart_info(NULL);
465*4882a593Smuzhiyun pxa_set_stuart_info(NULL);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
468*4882a593Smuzhiyun lpd270_flash_data[1].width = 4;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun /*
471*4882a593Smuzhiyun * System bus arbiter setting:
472*4882a593Smuzhiyun * - Core_Park
473*4882a593Smuzhiyun * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
474*4882a593Smuzhiyun */
475*4882a593Smuzhiyun ARB_CNTRL = ARB_CORE_PARK | 0x234;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
478*4882a593Smuzhiyun platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun pxa_set_ac97_info(NULL);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun if (lpd270_lcd_to_use != NULL)
483*4882a593Smuzhiyun pxa_set_fb_info(NULL, lpd270_lcd_to_use);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun pxa_set_ohci_info(&lpd270_ohci_platform_data);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun static struct map_desc lpd270_io_desc[] __initdata = {
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun .virtual = (unsigned long)LPD270_CPLD_VIRT,
492*4882a593Smuzhiyun .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
493*4882a593Smuzhiyun .length = LPD270_CPLD_SIZE,
494*4882a593Smuzhiyun .type = MT_DEVICE,
495*4882a593Smuzhiyun },
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun
lpd270_map_io(void)498*4882a593Smuzhiyun static void __init lpd270_map_io(void)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun pxa27x_map_io();
501*4882a593Smuzhiyun iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun /* for use I SRAM as framebuffer. */
504*4882a593Smuzhiyun PSLR |= 0x00000F04;
505*4882a593Smuzhiyun PCFR = 0x00000066;
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
509*4882a593Smuzhiyun /* Maintainer: Peter Barada */
510*4882a593Smuzhiyun .atag_offset = 0x100,
511*4882a593Smuzhiyun .map_io = lpd270_map_io,
512*4882a593Smuzhiyun .nr_irqs = LPD270_NR_IRQS,
513*4882a593Smuzhiyun .init_irq = lpd270_init_irq,
514*4882a593Smuzhiyun .handle_irq = pxa27x_handle_irq,
515*4882a593Smuzhiyun .init_time = pxa_timer_init,
516*4882a593Smuzhiyun .init_machine = lpd270_init,
517*4882a593Smuzhiyun .restart = pxa_restart,
518*4882a593Smuzhiyun MACHINE_END
519