1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_ARCH_RESET_H 3*4882a593Smuzhiyun #define __ASM_ARCH_RESET_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ 6*4882a593Smuzhiyun #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ 7*4882a593Smuzhiyun #define RESET_STATUS_LOWPOWER (1 << 2) /* Low Power/Sleep Exit */ 8*4882a593Smuzhiyun #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ 9*4882a593Smuzhiyun #define RESET_STATUS_ALL (0xf) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun extern unsigned int reset_status; 12*4882a593Smuzhiyun extern void clear_reset_status(unsigned int mask); 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /** 15*4882a593Smuzhiyun * init_gpio_reset() - register GPIO as reset generator 16*4882a593Smuzhiyun * @gpio: gpio nr 17*4882a593Smuzhiyun * @output: set gpio as output instead of input during normal work 18*4882a593Smuzhiyun * @level: output level 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun extern int init_gpio_reset(int gpio, int output, int level); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* __ASM_ARCH_RESET_H */ 23