1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_ARCH_REGS_UART_H 3*4882a593Smuzhiyun #define __ASM_ARCH_REGS_UART_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * UARTs 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Full Function UART (FFUART) */ 10*4882a593Smuzhiyun #define FFUART FFRBR 11*4882a593Smuzhiyun #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ 12*4882a593Smuzhiyun #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ 13*4882a593Smuzhiyun #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ 14*4882a593Smuzhiyun #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ 15*4882a593Smuzhiyun #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ 16*4882a593Smuzhiyun #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ 17*4882a593Smuzhiyun #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ 18*4882a593Smuzhiyun #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ 19*4882a593Smuzhiyun #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ 20*4882a593Smuzhiyun #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ 21*4882a593Smuzhiyun #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ 22*4882a593Smuzhiyun #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ 23*4882a593Smuzhiyun #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Bluetooth UART (BTUART) */ 26*4882a593Smuzhiyun #define BTUART BTRBR 27*4882a593Smuzhiyun #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ 28*4882a593Smuzhiyun #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ 29*4882a593Smuzhiyun #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ 30*4882a593Smuzhiyun #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ 31*4882a593Smuzhiyun #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ 32*4882a593Smuzhiyun #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ 33*4882a593Smuzhiyun #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ 34*4882a593Smuzhiyun #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ 35*4882a593Smuzhiyun #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ 36*4882a593Smuzhiyun #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ 37*4882a593Smuzhiyun #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ 38*4882a593Smuzhiyun #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ 39*4882a593Smuzhiyun #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Standard UART (STUART) */ 42*4882a593Smuzhiyun #define STUART STRBR 43*4882a593Smuzhiyun #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ 44*4882a593Smuzhiyun #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ 45*4882a593Smuzhiyun #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ 46*4882a593Smuzhiyun #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ 47*4882a593Smuzhiyun #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ 48*4882a593Smuzhiyun #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ 49*4882a593Smuzhiyun #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ 50*4882a593Smuzhiyun #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ 51*4882a593Smuzhiyun #define STMSR __REG(0x40700018) /* Reserved */ 52*4882a593Smuzhiyun #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ 53*4882a593Smuzhiyun #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ 54*4882a593Smuzhiyun #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ 55*4882a593Smuzhiyun #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Hardware UART (HWUART) */ 58*4882a593Smuzhiyun #define HWUART HWRBR 59*4882a593Smuzhiyun #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ 60*4882a593Smuzhiyun #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ 61*4882a593Smuzhiyun #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ 62*4882a593Smuzhiyun #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ 63*4882a593Smuzhiyun #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ 64*4882a593Smuzhiyun #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ 65*4882a593Smuzhiyun #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ 66*4882a593Smuzhiyun #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ 67*4882a593Smuzhiyun #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ 68*4882a593Smuzhiyun #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ 69*4882a593Smuzhiyun #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ 70*4882a593Smuzhiyun #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ 71*4882a593Smuzhiyun #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ 72*4882a593Smuzhiyun #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ 73*4882a593Smuzhiyun #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ 74*4882a593Smuzhiyun #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define IER_DMAE (1 << 7) /* DMA Requests Enable */ 77*4882a593Smuzhiyun #define IER_UUE (1 << 6) /* UART Unit Enable */ 78*4882a593Smuzhiyun #define IER_NRZE (1 << 5) /* NRZ coding Enable */ 79*4882a593Smuzhiyun #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ 80*4882a593Smuzhiyun #define IER_MIE (1 << 3) /* Modem Interrupt Enable */ 81*4882a593Smuzhiyun #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ 82*4882a593Smuzhiyun #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ 83*4882a593Smuzhiyun #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ 86*4882a593Smuzhiyun #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ 87*4882a593Smuzhiyun #define IIR_TOD (1 << 3) /* Time Out Detected */ 88*4882a593Smuzhiyun #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ 89*4882a593Smuzhiyun #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ 90*4882a593Smuzhiyun #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ 93*4882a593Smuzhiyun #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ 94*4882a593Smuzhiyun #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ 95*4882a593Smuzhiyun #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ 96*4882a593Smuzhiyun #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ 97*4882a593Smuzhiyun #define FCR_ITL_1 (0) 98*4882a593Smuzhiyun #define FCR_ITL_8 (FCR_ITL1) 99*4882a593Smuzhiyun #define FCR_ITL_16 (FCR_ITL2) 100*4882a593Smuzhiyun #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ 103*4882a593Smuzhiyun #define LCR_SB (1 << 6) /* Set Break */ 104*4882a593Smuzhiyun #define LCR_STKYP (1 << 5) /* Sticky Parity */ 105*4882a593Smuzhiyun #define LCR_EPS (1 << 4) /* Even Parity Select */ 106*4882a593Smuzhiyun #define LCR_PEN (1 << 3) /* Parity Enable */ 107*4882a593Smuzhiyun #define LCR_STB (1 << 2) /* Stop Bit */ 108*4882a593Smuzhiyun #define LCR_WLS1 (1 << 1) /* Word Length Select */ 109*4882a593Smuzhiyun #define LCR_WLS0 (1 << 0) /* Word Length Select */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define LSR_FIFOE (1 << 7) /* FIFO Error Status */ 112*4882a593Smuzhiyun #define LSR_TEMT (1 << 6) /* Transmitter Empty */ 113*4882a593Smuzhiyun #define LSR_TDRQ (1 << 5) /* Transmit Data Request */ 114*4882a593Smuzhiyun #define LSR_BI (1 << 4) /* Break Interrupt */ 115*4882a593Smuzhiyun #define LSR_FE (1 << 3) /* Framing Error */ 116*4882a593Smuzhiyun #define LSR_PE (1 << 2) /* Parity Error */ 117*4882a593Smuzhiyun #define LSR_OE (1 << 1) /* Overrun Error */ 118*4882a593Smuzhiyun #define LSR_DR (1 << 0) /* Data Ready */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define MCR_LOOP (1 << 4) 121*4882a593Smuzhiyun #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ 122*4882a593Smuzhiyun #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ 123*4882a593Smuzhiyun #define MCR_RTS (1 << 1) /* Request to Send */ 124*4882a593Smuzhiyun #define MCR_DTR (1 << 0) /* Data Terminal Ready */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define MSR_DCD (1 << 7) /* Data Carrier Detect */ 127*4882a593Smuzhiyun #define MSR_RI (1 << 6) /* Ring Indicator */ 128*4882a593Smuzhiyun #define MSR_DSR (1 << 5) /* Data Set Ready */ 129*4882a593Smuzhiyun #define MSR_CTS (1 << 4) /* Clear To Send */ 130*4882a593Smuzhiyun #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ 131*4882a593Smuzhiyun #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ 132*4882a593Smuzhiyun #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ 133*4882a593Smuzhiyun #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* 136*4882a593Smuzhiyun * IrSR (Infrared Selection Register) 137*4882a593Smuzhiyun */ 138*4882a593Smuzhiyun #define STISR_RXPL (1 << 4) /* Receive Data Polarity */ 139*4882a593Smuzhiyun #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ 140*4882a593Smuzhiyun #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ 141*4882a593Smuzhiyun #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ 142*4882a593Smuzhiyun #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #endif /* __ASM_ARCH_REGS_UART_H */ 145