1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_MACH_REGS_OST_H 3*4882a593Smuzhiyun #define __ASM_MACH_REGS_OST_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <mach/hardware.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * OS Timer & Match Registers 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define OSMR0 io_p2v(0x40A00000) /* */ 12*4882a593Smuzhiyun #define OSMR1 io_p2v(0x40A00004) /* */ 13*4882a593Smuzhiyun #define OSMR2 io_p2v(0x40A00008) /* */ 14*4882a593Smuzhiyun #define OSMR3 io_p2v(0x40A0000C) /* */ 15*4882a593Smuzhiyun #define OSMR4 io_p2v(0x40A00080) /* */ 16*4882a593Smuzhiyun #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */ 17*4882a593Smuzhiyun #define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */ 18*4882a593Smuzhiyun #define OMCR4 io_p2v(0x40A000C0) /* */ 19*4882a593Smuzhiyun #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */ 20*4882a593Smuzhiyun #define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */ 21*4882a593Smuzhiyun #define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define OSSR_M3 (1 << 3) /* Match status channel 3 */ 24*4882a593Smuzhiyun #define OSSR_M2 (1 << 2) /* Match status channel 2 */ 25*4882a593Smuzhiyun #define OSSR_M1 (1 << 1) /* Match status channel 1 */ 26*4882a593Smuzhiyun #define OSSR_M0 (1 << 0) /* Match status channel 0 */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define OWER_WME (1 << 0) /* Watchdog Match Enable */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ 31*4882a593Smuzhiyun #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ 32*4882a593Smuzhiyun #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ 33*4882a593Smuzhiyun #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif /* __ASM_MACH_REGS_OST_H */ 36