1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_ARCH_REGS_LCD_H 3*4882a593Smuzhiyun #define __ASM_ARCH_REGS_LCD_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <mach/bitfield.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * LCD Controller Registers and Bits Definitions 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #define LCCR0 (0x000) /* LCD Controller Control Register 0 */ 11*4882a593Smuzhiyun #define LCCR1 (0x004) /* LCD Controller Control Register 1 */ 12*4882a593Smuzhiyun #define LCCR2 (0x008) /* LCD Controller Control Register 2 */ 13*4882a593Smuzhiyun #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ 14*4882a593Smuzhiyun #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ 15*4882a593Smuzhiyun #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ 16*4882a593Smuzhiyun #define LCSR (0x038) /* LCD Controller Status Register 0 */ 17*4882a593Smuzhiyun #define LCSR1 (0x034) /* LCD Controller Status Register 1 */ 18*4882a593Smuzhiyun #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ 19*4882a593Smuzhiyun #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ 20*4882a593Smuzhiyun #define TMEDCR (0x044) /* TMED Control Register */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ 23*4882a593Smuzhiyun #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ 24*4882a593Smuzhiyun #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ 25*4882a593Smuzhiyun #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ 26*4882a593Smuzhiyun #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ 27*4882a593Smuzhiyun #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ 28*4882a593Smuzhiyun #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ 31*4882a593Smuzhiyun #define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ 32*4882a593Smuzhiyun #define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ 33*4882a593Smuzhiyun #define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CMDCR (0x100) /* Command Control Register */ 36*4882a593Smuzhiyun #define PRSR (0x104) /* Panel Read Status Register */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define LCCR3_PDFOR_0 (0 << 30) 41*4882a593Smuzhiyun #define LCCR3_PDFOR_1 (1 << 30) 42*4882a593Smuzhiyun #define LCCR3_PDFOR_2 (2 << 30) 43*4882a593Smuzhiyun #define LCCR3_PDFOR_3 (3 << 30) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define LCCR4_PAL_FOR_0 (0 << 15) 46*4882a593Smuzhiyun #define LCCR4_PAL_FOR_1 (1 << 15) 47*4882a593Smuzhiyun #define LCCR4_PAL_FOR_2 (2 << 15) 48*4882a593Smuzhiyun #define LCCR4_PAL_FOR_3 (3 << 15) 49*4882a593Smuzhiyun #define LCCR4_PAL_FOR_MASK (3 << 15) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ 52*4882a593Smuzhiyun #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ 53*4882a593Smuzhiyun #define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ 54*4882a593Smuzhiyun #define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ 55*4882a593Smuzhiyun #define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ 56*4882a593Smuzhiyun #define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ 57*4882a593Smuzhiyun #define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ 60*4882a593Smuzhiyun #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ 61*4882a593Smuzhiyun #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ 62*4882a593Smuzhiyun #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ 63*4882a593Smuzhiyun #define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */ 64*4882a593Smuzhiyun #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ 65*4882a593Smuzhiyun #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ 68*4882a593Smuzhiyun #define LCCR0_SFM (1 << 4) /* Start of frame mask */ 69*4882a593Smuzhiyun #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ 70*4882a593Smuzhiyun #define LCCR0_EFM (1 << 6) /* End of Frame mask */ 71*4882a593Smuzhiyun #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ 72*4882a593Smuzhiyun #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ 73*4882a593Smuzhiyun #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ 74*4882a593Smuzhiyun #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */ 75*4882a593Smuzhiyun #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */ 76*4882a593Smuzhiyun #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */ 77*4882a593Smuzhiyun #define LCCR0_DIS (1 << 10) /* LCD Disable */ 78*4882a593Smuzhiyun #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ 79*4882a593Smuzhiyun #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ 80*4882a593Smuzhiyun #define LCCR0_PDD_S 12 81*4882a593Smuzhiyun #define LCCR0_BM (1 << 20) /* Branch mask */ 82*4882a593Smuzhiyun #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ 83*4882a593Smuzhiyun #define LCCR0_LCDT (1 << 22) /* LCD panel type */ 84*4882a593Smuzhiyun #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ 85*4882a593Smuzhiyun #define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ 86*4882a593Smuzhiyun #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ 87*4882a593Smuzhiyun #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ 90*4882a593Smuzhiyun #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ 93*4882a593Smuzhiyun #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW)) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */ 96*4882a593Smuzhiyun #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW)) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ 99*4882a593Smuzhiyun #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW)) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ 102*4882a593Smuzhiyun #define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP)) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ 105*4882a593Smuzhiyun #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ 108*4882a593Smuzhiyun #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ 111*4882a593Smuzhiyun #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ 114*4882a593Smuzhiyun #define LCCR3_API_S 16 115*4882a593Smuzhiyun #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ 116*4882a593Smuzhiyun #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ 117*4882a593Smuzhiyun #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ 118*4882a593Smuzhiyun #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ 119*4882a593Smuzhiyun #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define LCCR3_OEP (1 << 23) /* Output Enable Polarity */ 122*4882a593Smuzhiyun #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ 123*4882a593Smuzhiyun #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define LCCR3_DPC (1 << 27) /* double pixel clock mode */ 126*4882a593Smuzhiyun #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ 127*4882a593Smuzhiyun #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define LCCR3_ACB Fld (8, 8) /* AC Bias */ 130*4882a593Smuzhiyun #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */ 133*4882a593Smuzhiyun #define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */ 136*4882a593Smuzhiyun #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */ 139*4882a593Smuzhiyun #define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */ 140*4882a593Smuzhiyun #define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */ 141*4882a593Smuzhiyun #define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define LCSR_LDD (1 << 0) /* LCD Disable Done */ 144*4882a593Smuzhiyun #define LCSR_SOF (1 << 1) /* Start of frame */ 145*4882a593Smuzhiyun #define LCSR_BER (1 << 2) /* Bus error */ 146*4882a593Smuzhiyun #define LCSR_ABC (1 << 3) /* AC Bias count */ 147*4882a593Smuzhiyun #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ 148*4882a593Smuzhiyun #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ 149*4882a593Smuzhiyun #define LCSR_OU (1 << 6) /* output FIFO underrun */ 150*4882a593Smuzhiyun #define LCSR_QD (1 << 7) /* quick disable */ 151*4882a593Smuzhiyun #define LCSR_EOF (1 << 8) /* end of frame */ 152*4882a593Smuzhiyun #define LCSR_BS (1 << 9) /* branch status */ 153*4882a593Smuzhiyun #define LCSR_SINT (1 << 10) /* subsequent interrupt */ 154*4882a593Smuzhiyun #define LCSR_RD_ST (1 << 11) /* read status */ 155*4882a593Smuzhiyun #define LCSR_CMD_INT (1 << 12) /* command interrupt */ 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ 158*4882a593Smuzhiyun #define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ 159*4882a593Smuzhiyun #define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ 160*4882a593Smuzhiyun #define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* overlay control registers */ 165*4882a593Smuzhiyun #define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ 166*4882a593Smuzhiyun #define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ 167*4882a593Smuzhiyun #define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ 168*4882a593Smuzhiyun #define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ 169*4882a593Smuzhiyun #define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ 170*4882a593Smuzhiyun #define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ 171*4882a593Smuzhiyun #define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun /* smartpanel related */ 174*4882a593Smuzhiyun #define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ 175*4882a593Smuzhiyun #define PRSR_A0 (1 << 8) /* Read Data Source */ 176*4882a593Smuzhiyun #define PRSR_ST_OK (1 << 9) /* Status OK */ 177*4882a593Smuzhiyun #define PRSR_CON_NT (1 << 10) /* Continue to Next Command */ 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define SMART_CMD_A0 (0x1 << 8) 180*4882a593Smuzhiyun #define SMART_CMD_READ_STATUS_REG (0x0 << 9) 181*4882a593Smuzhiyun #define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0) 182*4882a593Smuzhiyun #define SMART_CMD_WRITE_COMMAND (0x1 << 9) 183*4882a593Smuzhiyun #define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0) 184*4882a593Smuzhiyun #define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0) 185*4882a593Smuzhiyun #define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9) 186*4882a593Smuzhiyun #define SMART_CMD_NOOP (0x4 << 9) 187*4882a593Smuzhiyun #define SMART_CMD_INTERRUPT (0x5 << 9) 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) 190*4882a593Smuzhiyun #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* SMART_DELAY() is introduced for software controlled delay primitive which 193*4882a593Smuzhiyun * can be inserted between command sequences, unused command 0x6 is used here 194*4882a593Smuzhiyun * and delay ranges from 0ms ~ 255ms 195*4882a593Smuzhiyun */ 196*4882a593Smuzhiyun #define SMART_CMD_DELAY (0x6 << 9) 197*4882a593Smuzhiyun #define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) 198*4882a593Smuzhiyun #endif /* __ASM_ARCH_REGS_LCD_H */ 199