1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * PXA3xx specific register definitions 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2007 Marvell International Ltd. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_PXA3XX_REGS_H 11*4882a593Smuzhiyun #define __ASM_ARCH_PXA3XX_REGS_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <mach/hardware.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Oscillator Configuration Register (OSCC) 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define OSCC_PEN (1 << 11) /* 13MHz POUT */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Service Power Management Unit (MPMU) 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ 27*4882a593Smuzhiyun #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ 28*4882a593Smuzhiyun #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ 29*4882a593Smuzhiyun #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ 30*4882a593Smuzhiyun #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ 31*4882a593Smuzhiyun #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ 32*4882a593Smuzhiyun #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ 33*4882a593Smuzhiyun #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ 34*4882a593Smuzhiyun #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ 35*4882a593Smuzhiyun #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * Slave Power Management Unit 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ 41*4882a593Smuzhiyun #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ 42*4882a593Smuzhiyun #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ 43*4882a593Smuzhiyun #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ 44*4882a593Smuzhiyun #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ 45*4882a593Smuzhiyun #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ 46*4882a593Smuzhiyun #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ 47*4882a593Smuzhiyun #define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ 48*4882a593Smuzhiyun #define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ 49*4882a593Smuzhiyun #define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ 50*4882a593Smuzhiyun #define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ 51*4882a593Smuzhiyun #define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ 52*4882a593Smuzhiyun #define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ 53*4882a593Smuzhiyun #define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * Application Subsystem Configuration bits. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define ASCR_RDH (1 << 31) 59*4882a593Smuzhiyun #define ASCR_D1S (1 << 2) 60*4882a593Smuzhiyun #define ASCR_D2S (1 << 1) 61*4882a593Smuzhiyun #define ASCR_D3S (1 << 0) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * Application Reset Status bits. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define ARSR_GPR (1 << 3) 67*4882a593Smuzhiyun #define ARSR_LPMR (1 << 2) 68*4882a593Smuzhiyun #define ARSR_WDT (1 << 1) 69*4882a593Smuzhiyun #define ARSR_HWR (1 << 0) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * Application Subsystem Wake-Up bits. 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun #define ADXER_WRTC (1 << 31) /* RTC */ 75*4882a593Smuzhiyun #define ADXER_WOST (1 << 30) /* OS Timer */ 76*4882a593Smuzhiyun #define ADXER_WTSI (1 << 29) /* Touchscreen */ 77*4882a593Smuzhiyun #define ADXER_WUSBH (1 << 28) /* USB host */ 78*4882a593Smuzhiyun #define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ 79*4882a593Smuzhiyun #define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ 80*4882a593Smuzhiyun #define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ 81*4882a593Smuzhiyun #define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ 82*4882a593Smuzhiyun #define ADXER_WKP (1 << 21) /* Keypad */ 83*4882a593Smuzhiyun #define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ 84*4882a593Smuzhiyun #define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ 85*4882a593Smuzhiyun #define ADXER_WOTG (1 << 16) /* USBOTG input */ 86*4882a593Smuzhiyun #define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ 87*4882a593Smuzhiyun #define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ 88*4882a593Smuzhiyun #define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ 89*4882a593Smuzhiyun #define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ 90*4882a593Smuzhiyun #define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ 91*4882a593Smuzhiyun #define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ 92*4882a593Smuzhiyun #define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ 93*4882a593Smuzhiyun #define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ 94*4882a593Smuzhiyun #define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ 95*4882a593Smuzhiyun #define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ 96*4882a593Smuzhiyun #define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ 97*4882a593Smuzhiyun #define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ 98*4882a593Smuzhiyun #define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ 99*4882a593Smuzhiyun #define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ 100*4882a593Smuzhiyun #define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ 101*4882a593Smuzhiyun #define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* 104*4882a593Smuzhiyun * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun #define ADXR_L2 (1 << 8) 107*4882a593Smuzhiyun #define ADXR_R5 (1 << 5) 108*4882a593Smuzhiyun #define ADXR_R4 (1 << 4) 109*4882a593Smuzhiyun #define ADXR_R3 (1 << 3) 110*4882a593Smuzhiyun #define ADXR_R2 (1 << 2) 111*4882a593Smuzhiyun #define ADXR_R1 (1 << 1) 112*4882a593Smuzhiyun #define ADXR_R0 (1 << 0) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* 115*4882a593Smuzhiyun * Values for PWRMODE CP15 register 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun #define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ 118*4882a593Smuzhiyun #define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ 119*4882a593Smuzhiyun #define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ 120*4882a593Smuzhiyun #define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ 121*4882a593Smuzhiyun #define PXA3xx_PM_S0D0C1 0x01 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * Application Subsystem Clock 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ 127*4882a593Smuzhiyun #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ 128*4882a593Smuzhiyun #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ 129*4882a593Smuzhiyun #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ 130*4882a593Smuzhiyun #define CKENB __REG(0x41340010) /* B Clock Enable Register */ 131*4882a593Smuzhiyun #define CKENC __REG(0x41340024) /* C Clock Enable Register */ 132*4882a593Smuzhiyun #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ 135*4882a593Smuzhiyun #define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ 136*4882a593Smuzhiyun #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ 137*4882a593Smuzhiyun #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ 138*4882a593Smuzhiyun #define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ 141*4882a593Smuzhiyun #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ 142*4882a593Smuzhiyun #define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ 143*4882a593Smuzhiyun #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ 144*4882a593Smuzhiyun #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ 145*4882a593Smuzhiyun #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ 146*4882a593Smuzhiyun #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define ACCR_SMCFS(x) (((x) & 0x7) << 23) 149*4882a593Smuzhiyun #define ACCR_SFLFS(x) (((x) & 0x3) << 18) 150*4882a593Smuzhiyun #define ACCR_XSPCLK(x) (((x) & 0x3) << 16) 151*4882a593Smuzhiyun #define ACCR_HSS(x) (((x) & 0x3) << 14) 152*4882a593Smuzhiyun #define ACCR_DMCFS(x) (((x) & 0x3) << 12) 153*4882a593Smuzhiyun #define ACCR_XN(x) (((x) & 0x7) << 8) 154*4882a593Smuzhiyun #define ACCR_XL(x) ((x) & 0x1f) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* 157*4882a593Smuzhiyun * Clock Enable Bit 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun #define CKEN_LCD 1 /* < LCD Clock Enable */ 160*4882a593Smuzhiyun #define CKEN_USBH 2 /* < USB host clock enable */ 161*4882a593Smuzhiyun #define CKEN_CAMERA 3 /* < Camera interface clock enable */ 162*4882a593Smuzhiyun #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ 163*4882a593Smuzhiyun #define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ 164*4882a593Smuzhiyun #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ 165*4882a593Smuzhiyun #define CKEN_SMC 9 /* < Static Memory Controller clock enable */ 166*4882a593Smuzhiyun #define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ 167*4882a593Smuzhiyun #define CKEN_BOOT 11 /* < Boot rom clock enable */ 168*4882a593Smuzhiyun #define CKEN_MMC1 12 /* < MMC1 Clock enable */ 169*4882a593Smuzhiyun #define CKEN_MMC2 13 /* < MMC2 clock enable */ 170*4882a593Smuzhiyun #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ 171*4882a593Smuzhiyun #define CKEN_CIR 15 /* < Consumer IR Clock Enable */ 172*4882a593Smuzhiyun #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ 173*4882a593Smuzhiyun #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ 174*4882a593Smuzhiyun #define CKEN_TPM 19 /* < TPM clock enable */ 175*4882a593Smuzhiyun #define CKEN_UDC 20 /* < UDC clock enable */ 176*4882a593Smuzhiyun #define CKEN_BTUART 21 /* < BTUART clock enable */ 177*4882a593Smuzhiyun #define CKEN_FFUART 22 /* < FFUART clock enable */ 178*4882a593Smuzhiyun #define CKEN_STUART 23 /* < STUART clock enable */ 179*4882a593Smuzhiyun #define CKEN_AC97 24 /* < AC97 clock enable */ 180*4882a593Smuzhiyun #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ 181*4882a593Smuzhiyun #define CKEN_SSP1 26 /* < SSP1 clock enable */ 182*4882a593Smuzhiyun #define CKEN_SSP2 27 /* < SSP2 clock enable */ 183*4882a593Smuzhiyun #define CKEN_SSP3 28 /* < SSP3 clock enable */ 184*4882a593Smuzhiyun #define CKEN_SSP4 29 /* < SSP4 clock enable */ 185*4882a593Smuzhiyun #define CKEN_MSL0 30 /* < MSL0 clock enable */ 186*4882a593Smuzhiyun #define CKEN_PWM0 32 /* < PWM[0] clock enable */ 187*4882a593Smuzhiyun #define CKEN_PWM1 33 /* < PWM[1] clock enable */ 188*4882a593Smuzhiyun #define CKEN_I2C 36 /* < I2C clock enable */ 189*4882a593Smuzhiyun #define CKEN_INTC 38 /* < Interrupt controller clock enable */ 190*4882a593Smuzhiyun #define CKEN_GPIO 39 /* < GPIO clock enable */ 191*4882a593Smuzhiyun #define CKEN_1WIRE 40 /* < 1-wire clock enable */ 192*4882a593Smuzhiyun #define CKEN_HSIO2 41 /* < HSIO2 clock enable */ 193*4882a593Smuzhiyun #define CKEN_MINI_IM 48 /* < Mini-IM */ 194*4882a593Smuzhiyun #define CKEN_MINI_LCD 49 /* < Mini LCD */ 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define CKEN_MMC3 5 /* < MMC3 Clock Enable */ 197*4882a593Smuzhiyun #define CKEN_MVED 43 /* < MVED clock enable */ 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ 200*4882a593Smuzhiyun #define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ 201*4882a593Smuzhiyun #define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #endif /* __ASM_ARCH_PXA3XX_REGS_H */ 204