1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * GPIO and IRQ definitions for HP iPAQ hx4700 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2008 Philipp Zabel 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _HX4700_H_ 9*4882a593Smuzhiyun #define _HX4700_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/gpio.h> 12*4882a593Smuzhiyun #include <linux/mfd/asic3.h> 13*4882a593Smuzhiyun #include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO 16*4882a593Smuzhiyun #define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) 17*4882a593Smuzhiyun #define HX4700_NR_IRQS (IRQ_BOARD_START + 70) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * PXA GPIOs 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define GPIO0_HX4700_nKEY_POWER 0 24*4882a593Smuzhiyun #define GPIO12_HX4700_ASIC3_IRQ 12 25*4882a593Smuzhiyun #define GPIO13_HX4700_W3220_IRQ 13 26*4882a593Smuzhiyun #define GPIO14_HX4700_nWLAN_IRQ 14 27*4882a593Smuzhiyun #define GPIO18_HX4700_RDY 18 28*4882a593Smuzhiyun #define GPIO22_HX4700_LCD_RL 22 29*4882a593Smuzhiyun #define GPIO27_HX4700_CODEC_ON 27 30*4882a593Smuzhiyun #define GPIO32_HX4700_RS232_ON 32 31*4882a593Smuzhiyun #define GPIO52_HX4700_CPU_nBATT_FAULT 52 32*4882a593Smuzhiyun #define GPIO58_HX4700_TSC2046_nPENIRQ 58 33*4882a593Smuzhiyun #define GPIO59_HX4700_LCD_PC1 59 34*4882a593Smuzhiyun #define GPIO60_HX4700_CF_RNB 60 35*4882a593Smuzhiyun #define GPIO61_HX4700_W3220_nRESET 61 36*4882a593Smuzhiyun #define GPIO62_HX4700_LCD_nRESET 62 37*4882a593Smuzhiyun #define GPIO63_HX4700_CPU_SS_nRESET 63 38*4882a593Smuzhiyun #define GPIO65_HX4700_TSC2046_PEN_PU 65 39*4882a593Smuzhiyun #define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66 40*4882a593Smuzhiyun #define GPIO67_HX4700_EUART_PS 67 41*4882a593Smuzhiyun #define GPIO70_HX4700_LCD_SLIN1 70 42*4882a593Smuzhiyun #define GPIO71_HX4700_ASIC3_nRESET 71 43*4882a593Smuzhiyun #define GPIO72_HX4700_BQ24022_nCHARGE_EN 72 44*4882a593Smuzhiyun #define GPIO73_HX4700_LCD_UD_1 73 45*4882a593Smuzhiyun #define GPIO75_HX4700_EARPHONE_nDET 75 46*4882a593Smuzhiyun #define GPIO76_HX4700_USBC_PUEN 76 47*4882a593Smuzhiyun #define GPIO81_HX4700_CPU_GP_nRESET 81 48*4882a593Smuzhiyun #define GPIO82_HX4700_EUART_RESET 82 49*4882a593Smuzhiyun #define GPIO83_HX4700_WLAN_nRESET 83 50*4882a593Smuzhiyun #define GPIO84_HX4700_LCD_SQN 84 51*4882a593Smuzhiyun #define GPIO85_HX4700_nPCE1 85 52*4882a593Smuzhiyun #define GPIO88_HX4700_TSC2046_CS 88 53*4882a593Smuzhiyun #define GPIO91_HX4700_FLASH_VPEN 91 54*4882a593Smuzhiyun #define GPIO92_HX4700_HP_DRIVER 92 55*4882a593Smuzhiyun #define GPIO93_HX4700_EUART_INT 93 56*4882a593Smuzhiyun #define GPIO94_HX4700_KEY_MAIL 94 57*4882a593Smuzhiyun #define GPIO95_HX4700_BATT_OFF 95 58*4882a593Smuzhiyun #define GPIO96_HX4700_BQ24022_ISET2 96 59*4882a593Smuzhiyun #define GPIO97_HX4700_nBL_DETECT 97 60*4882a593Smuzhiyun #define GPIO99_HX4700_KEY_CONTACTS 99 61*4882a593Smuzhiyun #define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */ 62*4882a593Smuzhiyun #define GPIO102_HX4700_SYNAPTICS_POWER_ON 102 63*4882a593Smuzhiyun #define GPIO103_HX4700_SYNAPTICS_INT 103 64*4882a593Smuzhiyun #define GPIO105_HX4700_nIR_ON 105 65*4882a593Smuzhiyun #define GPIO106_HX4700_CPU_BT_nRESET 106 66*4882a593Smuzhiyun #define GPIO107_HX4700_SPK_nSD 107 67*4882a593Smuzhiyun #define GPIO109_HX4700_CODEC_nPDN 109 68*4882a593Smuzhiyun #define GPIO110_HX4700_LCD_LVDD_3V3_ON 110 69*4882a593Smuzhiyun #define GPIO111_HX4700_LCD_AVDD_3V3_ON 111 70*4882a593Smuzhiyun #define GPIO112_HX4700_LCD_N2V7_7V3_ON 112 71*4882a593Smuzhiyun #define GPIO114_HX4700_CF_RESET 114 72*4882a593Smuzhiyun #define GPIO116_HX4700_CPU_HW_nRESET 116 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * ASIC3 GPIOs 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32) 79*4882a593Smuzhiyun #define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define GPIOC0_LED_RED (GPIOC_BASE + 0) 82*4882a593Smuzhiyun #define GPIOC1_LED_GREEN (GPIOC_BASE + 1) 83*4882a593Smuzhiyun #define GPIOC2_LED_BLUE (GPIOC_BASE + 2) 84*4882a593Smuzhiyun #define GPIOC3_nSD_CS (GPIOC_BASE + 3) 85*4882a593Smuzhiyun #define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */ 86*4882a593Smuzhiyun #define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */ 87*4882a593Smuzhiyun #define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */ 88*4882a593Smuzhiyun #define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */ 89*4882a593Smuzhiyun #define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */ 90*4882a593Smuzhiyun #define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */ 91*4882a593Smuzhiyun #define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */ 92*4882a593Smuzhiyun #define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */ 93*4882a593Smuzhiyun #define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */ 94*4882a593Smuzhiyun #define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */ 95*4882a593Smuzhiyun #define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */ 96*4882a593Smuzhiyun #define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */ 99*4882a593Smuzhiyun #define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1) 100*4882a593Smuzhiyun #define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2) 101*4882a593Smuzhiyun #define GPIOD3_nKEY_HOME (GPIOD_BASE + 3) 102*4882a593Smuzhiyun #define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */ 103*4882a593Smuzhiyun #define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */ 104*4882a593Smuzhiyun #define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6) 105*4882a593Smuzhiyun #define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7) 106*4882a593Smuzhiyun #define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */ 107*4882a593Smuzhiyun #define GPIOD9_nAC_IN (GPIOD_BASE + 9) 108*4882a593Smuzhiyun #define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */ 109*4882a593Smuzhiyun #define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */ 110*4882a593Smuzhiyun #define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */ 111*4882a593Smuzhiyun #define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */ 112*4882a593Smuzhiyun #define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14) 113*4882a593Smuzhiyun #define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* 116*4882a593Smuzhiyun * EGPIOs 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */ 120*4882a593Smuzhiyun #define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */ 121*4882a593Smuzhiyun #define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */ 122*4882a593Smuzhiyun #define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */ 123*4882a593Smuzhiyun #define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */ 124*4882a593Smuzhiyun #define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */ 125*4882a593Smuzhiyun #define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */ 126*4882a593Smuzhiyun #define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */ 127*4882a593Smuzhiyun #define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif /* _HX4700_H_ */ 130