1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_MACH_ADDR_MAP_H 3*4882a593Smuzhiyun #define __ASM_MACH_ADDR_MAP_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Chip Selects 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #define PXA_CS0_PHYS 0x00000000 9*4882a593Smuzhiyun #define PXA_CS1_PHYS 0x04000000 10*4882a593Smuzhiyun #define PXA_CS2_PHYS 0x08000000 11*4882a593Smuzhiyun #define PXA_CS3_PHYS 0x0C000000 12*4882a593Smuzhiyun #define PXA_CS4_PHYS 0x10000000 13*4882a593Smuzhiyun #define PXA_CS5_PHYS 0x14000000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ 16*4882a593Smuzhiyun #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ 17*4882a593Smuzhiyun #define PXA3xx_CS2_PHYS 0x10000000 18*4882a593Smuzhiyun #define PXA3xx_CS3_PHYS 0x14000000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Peripheral Bus 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define PERIPH_PHYS 0x40000000 24*4882a593Smuzhiyun #define PERIPH_VIRT IOMEM(0xf2000000) 25*4882a593Smuzhiyun #define PERIPH_SIZE 0x02000000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define PXA2XX_SMEMC_PHYS 0x48000000 31*4882a593Smuzhiyun #define PXA3XX_SMEMC_PHYS 0x4a000000 32*4882a593Smuzhiyun #define SMEMC_VIRT IOMEM(0xf6000000) 33*4882a593Smuzhiyun #define SMEMC_SIZE 0x00100000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Dynamic Memory Controller (only on PXA3xx) 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define DMEMC_PHYS 0x48100000 39*4882a593Smuzhiyun #define DMEMC_VIRT IOMEM(0xf6100000) 40*4882a593Smuzhiyun #define DMEMC_SIZE 0x00100000 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * Reserved space for low level debug virtual addresses within 44*4882a593Smuzhiyun * 0xf6200000..0xf6201000 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * DFI Bus for NAND, PXA3xx only 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define NAND_PHYS 0x43100000 51*4882a593Smuzhiyun #define NAND_VIRT IOMEM(0xf6300000) 52*4882a593Smuzhiyun #define NAND_SIZE 0x00100000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Internal Memory Controller (PXA27x and later) 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define IMEMC_PHYS 0x58000000 58*4882a593Smuzhiyun #define IMEMC_VIRT IOMEM(0xfe000000) 59*4882a593Smuzhiyun #define IMEMC_SIZE 0x00100000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* __ASM_MACH_ADDR_MAP_H */ 62