xref: /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/h5000.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Hardware definitions for HP iPAQ h5xxx Handheld Computers
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2000-2003  Hewlett-Packard Company.
6*4882a593Smuzhiyun  * Copyright 2002       Jamey Hicks <jamey.hicks@hp.com>
7*4882a593Smuzhiyun  * Copyright 2004-2005  Phil Blundell <pb@handhelds.org>
8*4882a593Smuzhiyun  * Copyright 2007-2008  Anton Vorontsov <cbouatmailru@gmail.com>
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
11*4882a593Smuzhiyun  * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
12*4882a593Smuzhiyun  * FITNESS FOR ANY PARTICULAR PURPOSE.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * Author: Jamey Hicks.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
21*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
22*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include <asm/mach-types.h>
25*4882a593Smuzhiyun #include <asm/mach/arch.h>
26*4882a593Smuzhiyun #include <asm/mach/map.h>
27*4882a593Smuzhiyun #include <asm/irq.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #include "pxa25x.h"
30*4882a593Smuzhiyun #include "h5000.h"
31*4882a593Smuzhiyun #include "udc.h"
32*4882a593Smuzhiyun #include <mach/smemc.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #include "generic.h"
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun  * Flash
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static struct mtd_partition h5000_flash0_partitions[] = {
41*4882a593Smuzhiyun 	{
42*4882a593Smuzhiyun 		.name = "bootldr",
43*4882a593Smuzhiyun 		.size = 0x00040000,
44*4882a593Smuzhiyun 		.offset = 0,
45*4882a593Smuzhiyun 		.mask_flags = MTD_WRITEABLE,
46*4882a593Smuzhiyun 	},
47*4882a593Smuzhiyun 	{
48*4882a593Smuzhiyun 		.name = "root",
49*4882a593Smuzhiyun 		.size = MTDPART_SIZ_FULL,
50*4882a593Smuzhiyun 		.offset = MTDPART_OFS_APPEND,
51*4882a593Smuzhiyun 	},
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun static struct mtd_partition h5000_flash1_partitions[] = {
55*4882a593Smuzhiyun 	{
56*4882a593Smuzhiyun 		.name = "second root",
57*4882a593Smuzhiyun 		.size = SZ_16M - 0x00040000,
58*4882a593Smuzhiyun 		.offset = 0,
59*4882a593Smuzhiyun 	},
60*4882a593Smuzhiyun 	{
61*4882a593Smuzhiyun 		.name = "asset",
62*4882a593Smuzhiyun 		.size = MTDPART_SIZ_FULL,
63*4882a593Smuzhiyun 		.offset = MTDPART_OFS_APPEND,
64*4882a593Smuzhiyun 		.mask_flags = MTD_WRITEABLE,
65*4882a593Smuzhiyun 	},
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun static struct physmap_flash_data h5000_flash0_data = {
69*4882a593Smuzhiyun 	.width = 4,
70*4882a593Smuzhiyun 	.parts = h5000_flash0_partitions,
71*4882a593Smuzhiyun 	.nr_parts = ARRAY_SIZE(h5000_flash0_partitions),
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun static struct physmap_flash_data h5000_flash1_data = {
75*4882a593Smuzhiyun 	.width = 4,
76*4882a593Smuzhiyun 	.parts = h5000_flash1_partitions,
77*4882a593Smuzhiyun 	.nr_parts = ARRAY_SIZE(h5000_flash1_partitions),
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun static struct resource h5000_flash0_resources = {
81*4882a593Smuzhiyun 	.start = PXA_CS0_PHYS,
82*4882a593Smuzhiyun 	.end = PXA_CS0_PHYS + SZ_32M - 1,
83*4882a593Smuzhiyun 	.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static struct resource h5000_flash1_resources = {
87*4882a593Smuzhiyun 	.start = PXA_CS0_PHYS + SZ_32M,
88*4882a593Smuzhiyun 	.end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1,
89*4882a593Smuzhiyun 	.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun static struct platform_device h5000_flash[] = {
93*4882a593Smuzhiyun 	{
94*4882a593Smuzhiyun 		.name = "physmap-flash",
95*4882a593Smuzhiyun 		.id = 0,
96*4882a593Smuzhiyun 		.resource = &h5000_flash0_resources,
97*4882a593Smuzhiyun 		.num_resources = 1,
98*4882a593Smuzhiyun 		.dev = {
99*4882a593Smuzhiyun 			.platform_data = &h5000_flash0_data,
100*4882a593Smuzhiyun 		},
101*4882a593Smuzhiyun 	},
102*4882a593Smuzhiyun 	{
103*4882a593Smuzhiyun 		.name = "physmap-flash",
104*4882a593Smuzhiyun 		.id = 1,
105*4882a593Smuzhiyun 		.resource = &h5000_flash1_resources,
106*4882a593Smuzhiyun 		.num_resources = 1,
107*4882a593Smuzhiyun 		.dev = {
108*4882a593Smuzhiyun 			.platform_data = &h5000_flash1_data,
109*4882a593Smuzhiyun 		},
110*4882a593Smuzhiyun 	},
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun  * USB Device Controller
115*4882a593Smuzhiyun  */
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun static struct pxa2xx_udc_mach_info h5000_udc_mach_info __initdata = {
118*4882a593Smuzhiyun 	.gpio_pullup = H5000_GPIO_USB_PULLUP,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /*
122*4882a593Smuzhiyun  * GPIO setup
123*4882a593Smuzhiyun  */
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun static unsigned long h5000_pin_config[] __initdata = {
126*4882a593Smuzhiyun 	/* Crystal and Clock Signals */
127*4882a593Smuzhiyun 	GPIO12_32KHz,
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/* SDRAM and Static Memory I/O Signals */
130*4882a593Smuzhiyun 	GPIO15_nCS_1,
131*4882a593Smuzhiyun 	GPIO78_nCS_2,
132*4882a593Smuzhiyun 	GPIO79_nCS_3,
133*4882a593Smuzhiyun 	GPIO80_nCS_4,
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* FFUART */
136*4882a593Smuzhiyun 	GPIO34_FFUART_RXD,
137*4882a593Smuzhiyun 	GPIO35_FFUART_CTS,
138*4882a593Smuzhiyun 	GPIO36_FFUART_DCD,
139*4882a593Smuzhiyun 	GPIO37_FFUART_DSR,
140*4882a593Smuzhiyun 	GPIO38_FFUART_RI,
141*4882a593Smuzhiyun 	GPIO39_FFUART_TXD,
142*4882a593Smuzhiyun 	GPIO40_FFUART_DTR,
143*4882a593Smuzhiyun 	GPIO41_FFUART_RTS,
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	/* BTUART */
146*4882a593Smuzhiyun 	GPIO42_BTUART_RXD,
147*4882a593Smuzhiyun 	GPIO43_BTUART_TXD,
148*4882a593Smuzhiyun 	GPIO44_BTUART_CTS,
149*4882a593Smuzhiyun 	GPIO45_BTUART_RTS,
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	/* SSP1 */
152*4882a593Smuzhiyun 	GPIO23_SSP1_SCLK,
153*4882a593Smuzhiyun 	GPIO25_SSP1_TXD,
154*4882a593Smuzhiyun 	GPIO26_SSP1_RXD,
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	/* I2S */
157*4882a593Smuzhiyun 	GPIO28_I2S_BITCLK_OUT,
158*4882a593Smuzhiyun 	GPIO29_I2S_SDATA_IN,
159*4882a593Smuzhiyun 	GPIO30_I2S_SDATA_OUT,
160*4882a593Smuzhiyun 	GPIO31_I2S_SYNC,
161*4882a593Smuzhiyun 	GPIO32_I2S_SYSCLK,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /*
165*4882a593Smuzhiyun  * Localbus setup:
166*4882a593Smuzhiyun  * CS0: Flash;
167*4882a593Smuzhiyun  * CS1: MediaQ chip, select 16-bit bus and vlio;
168*4882a593Smuzhiyun  * CS5: SAMCOP.
169*4882a593Smuzhiyun  */
170*4882a593Smuzhiyun 
fix_msc(void)171*4882a593Smuzhiyun static void fix_msc(void)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	__raw_writel(0x129c24f2, MSC0);
174*4882a593Smuzhiyun 	__raw_writel(0x7ff424fa, MSC1);
175*4882a593Smuzhiyun 	__raw_writel(0x7ff47ff4, MSC2);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	__raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /*
181*4882a593Smuzhiyun  * Platform devices
182*4882a593Smuzhiyun  */
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun static struct platform_device *devices[] __initdata = {
185*4882a593Smuzhiyun 	&h5000_flash[0],
186*4882a593Smuzhiyun 	&h5000_flash[1],
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
h5000_init(void)189*4882a593Smuzhiyun static void __init h5000_init(void)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	fix_msc();
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config));
194*4882a593Smuzhiyun 	pxa_set_ffuart_info(NULL);
195*4882a593Smuzhiyun 	pxa_set_btuart_info(NULL);
196*4882a593Smuzhiyun 	pxa_set_stuart_info(NULL);
197*4882a593Smuzhiyun 	pxa_set_udc_info(&h5000_udc_mach_info);
198*4882a593Smuzhiyun 	platform_add_devices(ARRAY_AND_SIZE(devices));
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun MACHINE_START(H5400, "HP iPAQ H5000")
202*4882a593Smuzhiyun 	.atag_offset = 0x100,
203*4882a593Smuzhiyun 	.map_io = pxa25x_map_io,
204*4882a593Smuzhiyun 	.nr_irqs = PXA_NR_IRQS,
205*4882a593Smuzhiyun 	.init_irq = pxa25x_init_irq,
206*4882a593Smuzhiyun 	.handle_irq = pxa25x_handle_irq,
207*4882a593Smuzhiyun 	.init_time	= pxa_timer_init,
208*4882a593Smuzhiyun 	.init_machine = h5000_init,
209*4882a593Smuzhiyun 	.restart	= pxa_restart,
210*4882a593Smuzhiyun MACHINE_END
211