1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/arch/arm/mach-pxa/generic.c 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Nicolas Pitre 6*4882a593Smuzhiyun * Created: Jun 15, 2001 7*4882a593Smuzhiyun * Copyright: MontaVista Software Inc. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Code common to all PXA machines. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Since this file should be linked before any other machine specific file, 12*4882a593Smuzhiyun * the __initcall() here will be executed first. This serves as default 13*4882a593Smuzhiyun * initialization stuff for PXA machines which can be overridden later if 14*4882a593Smuzhiyun * need be. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #include <linux/gpio.h> 17*4882a593Smuzhiyun #include <linux/module.h> 18*4882a593Smuzhiyun #include <linux/kernel.h> 19*4882a593Smuzhiyun #include <linux/init.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include <mach/hardware.h> 22*4882a593Smuzhiyun #include <asm/mach/map.h> 23*4882a593Smuzhiyun #include <asm/mach-types.h> 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #include <mach/irqs.h> 26*4882a593Smuzhiyun #include <mach/reset.h> 27*4882a593Smuzhiyun #include <mach/smemc.h> 28*4882a593Smuzhiyun #include <mach/pxa3xx-regs.h> 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #include "generic.h" 31*4882a593Smuzhiyun #include <clocksource/pxa.h> 32*4882a593Smuzhiyun clear_reset_status(unsigned int mask)33*4882a593Smuzhiyunvoid clear_reset_status(unsigned int mask) 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun if (cpu_is_pxa2xx()) 36*4882a593Smuzhiyun pxa2xx_clear_reset_status(mask); 37*4882a593Smuzhiyun else { 38*4882a593Smuzhiyun /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 39*4882a593Smuzhiyun ARSR = mask; 40*4882a593Smuzhiyun } 41*4882a593Smuzhiyun } 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * For non device-tree builds, keep legacy timer init 45*4882a593Smuzhiyun */ pxa_timer_init(void)46*4882a593Smuzhiyunvoid __init pxa_timer_init(void) 47*4882a593Smuzhiyun { 48*4882a593Smuzhiyun if (cpu_is_pxa25x()) 49*4882a593Smuzhiyun pxa25x_clocks_init(); 50*4882a593Smuzhiyun if (cpu_is_pxa27x()) 51*4882a593Smuzhiyun pxa27x_clocks_init(); 52*4882a593Smuzhiyun if (cpu_is_pxa3xx()) 53*4882a593Smuzhiyun pxa3xx_clocks_init(); 54*4882a593Smuzhiyun pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000)); 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Get the clock frequency as reflected by CCCR and the turbo flag. 59*4882a593Smuzhiyun * We assume these values have been applied via a fcs. 60*4882a593Smuzhiyun * If info is not 0 we also display the current settings. 61*4882a593Smuzhiyun */ get_clk_frequency_khz(int info)62*4882a593Smuzhiyununsigned int get_clk_frequency_khz(int info) 63*4882a593Smuzhiyun { 64*4882a593Smuzhiyun if (cpu_is_pxa25x()) 65*4882a593Smuzhiyun return pxa25x_get_clk_frequency_khz(info); 66*4882a593Smuzhiyun else if (cpu_is_pxa27x()) 67*4882a593Smuzhiyun return pxa27x_get_clk_frequency_khz(info); 68*4882a593Smuzhiyun return 0; 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun EXPORT_SYMBOL(get_clk_frequency_khz); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * Intel PXA2xx internal register mapping. 74*4882a593Smuzhiyun * 75*4882a593Smuzhiyun * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table 76*4882a593Smuzhiyun * and cache flush area. 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun static struct map_desc common_io_desc[] __initdata = { 79*4882a593Smuzhiyun { /* Devs */ 80*4882a593Smuzhiyun .virtual = (unsigned long)PERIPH_VIRT, 81*4882a593Smuzhiyun .pfn = __phys_to_pfn(PERIPH_PHYS), 82*4882a593Smuzhiyun .length = PERIPH_SIZE, 83*4882a593Smuzhiyun .type = MT_DEVICE 84*4882a593Smuzhiyun } 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun pxa_map_io(void)87*4882a593Smuzhiyunvoid __init pxa_map_io(void) 88*4882a593Smuzhiyun { 89*4882a593Smuzhiyun debug_ll_io_init(); 90*4882a593Smuzhiyun iotable_init(ARRAY_AND_SIZE(common_io_desc)); 91*4882a593Smuzhiyun } 92