xref: /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/cm-x300.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * linux/arch/arm/mach-pxa/cm-x300.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Support for the CompuLab CM-X300 modules
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2008,2009 CompuLab Ltd.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Mike Rapoport <mike@compulab.co.il>
10*4882a593Smuzhiyun  * Igor Grinberg <grinberg@compulab.co.il>
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun #define pr_fmt(fmt) "%s: " fmt, __func__
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/clk.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <linux/gpio.h>
23*4882a593Smuzhiyun #include <linux/gpio/machine.h>
24*4882a593Smuzhiyun #include <linux/dm9000.h>
25*4882a593Smuzhiyun #include <linux/leds.h>
26*4882a593Smuzhiyun #include <linux/platform_data/rtc-v3020.h>
27*4882a593Smuzhiyun #include <linux/pwm.h>
28*4882a593Smuzhiyun #include <linux/pwm_backlight.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #include <linux/i2c.h>
31*4882a593Smuzhiyun #include <linux/platform_data/pca953x.h>
32*4882a593Smuzhiyun #include <linux/platform_data/i2c-pxa.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #include <linux/mfd/da903x.h>
35*4882a593Smuzhiyun #include <linux/regulator/machine.h>
36*4882a593Smuzhiyun #include <linux/power_supply.h>
37*4882a593Smuzhiyun #include <linux/apm-emulation.h>
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #include <linux/spi/spi.h>
40*4882a593Smuzhiyun #include <linux/spi/spi_gpio.h>
41*4882a593Smuzhiyun #include <linux/spi/tdo24m.h>
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #include <asm/mach-types.h>
44*4882a593Smuzhiyun #include <asm/mach/arch.h>
45*4882a593Smuzhiyun #include <asm/setup.h>
46*4882a593Smuzhiyun #include <asm/system_info.h>
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #include "pxa300.h"
49*4882a593Smuzhiyun #include "pxa27x-udc.h"
50*4882a593Smuzhiyun #include <linux/platform_data/video-pxafb.h>
51*4882a593Smuzhiyun #include <linux/platform_data/mmc-pxamci.h>
52*4882a593Smuzhiyun #include <linux/platform_data/usb-ohci-pxa27x.h>
53*4882a593Smuzhiyun #include <linux/platform_data/mtd-nand-pxa3xx.h>
54*4882a593Smuzhiyun #include <mach/audio.h>
55*4882a593Smuzhiyun #include <linux/platform_data/usb-pxa3xx-ulpi.h>
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #include <asm/mach/map.h>
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #include "generic.h"
60*4882a593Smuzhiyun #include "devices.h"
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define CM_X300_ETH_PHYS	0x08000010
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define GPIO82_MMC_IRQ		(82)
65*4882a593Smuzhiyun #define GPIO85_MMC_WP		(85)
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define	CM_X300_MMC_IRQ		PXA_GPIO_TO_IRQ(GPIO82_MMC_IRQ)
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define GPIO95_RTC_CS		(95)
70*4882a593Smuzhiyun #define GPIO96_RTC_WR		(96)
71*4882a593Smuzhiyun #define GPIO97_RTC_RD		(97)
72*4882a593Smuzhiyun #define GPIO98_RTC_IO		(98)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define GPIO_ULPI_PHY_RST	(127)
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
77*4882a593Smuzhiyun 	/* LCD */
78*4882a593Smuzhiyun 	GPIO54_LCD_LDD_0,
79*4882a593Smuzhiyun 	GPIO55_LCD_LDD_1,
80*4882a593Smuzhiyun 	GPIO56_LCD_LDD_2,
81*4882a593Smuzhiyun 	GPIO57_LCD_LDD_3,
82*4882a593Smuzhiyun 	GPIO58_LCD_LDD_4,
83*4882a593Smuzhiyun 	GPIO59_LCD_LDD_5,
84*4882a593Smuzhiyun 	GPIO60_LCD_LDD_6,
85*4882a593Smuzhiyun 	GPIO61_LCD_LDD_7,
86*4882a593Smuzhiyun 	GPIO62_LCD_LDD_8,
87*4882a593Smuzhiyun 	GPIO63_LCD_LDD_9,
88*4882a593Smuzhiyun 	GPIO64_LCD_LDD_10,
89*4882a593Smuzhiyun 	GPIO65_LCD_LDD_11,
90*4882a593Smuzhiyun 	GPIO66_LCD_LDD_12,
91*4882a593Smuzhiyun 	GPIO67_LCD_LDD_13,
92*4882a593Smuzhiyun 	GPIO68_LCD_LDD_14,
93*4882a593Smuzhiyun 	GPIO69_LCD_LDD_15,
94*4882a593Smuzhiyun 	GPIO72_LCD_FCLK,
95*4882a593Smuzhiyun 	GPIO73_LCD_LCLK,
96*4882a593Smuzhiyun 	GPIO74_LCD_PCLK,
97*4882a593Smuzhiyun 	GPIO75_LCD_BIAS,
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	/* BTUART */
100*4882a593Smuzhiyun 	GPIO111_UART2_RTS,
101*4882a593Smuzhiyun 	GPIO112_UART2_RXD | MFP_LPM_EDGE_FALL,
102*4882a593Smuzhiyun 	GPIO113_UART2_TXD,
103*4882a593Smuzhiyun 	GPIO114_UART2_CTS | MFP_LPM_EDGE_BOTH,
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/* STUART */
106*4882a593Smuzhiyun 	GPIO109_UART3_TXD,
107*4882a593Smuzhiyun 	GPIO110_UART3_RXD | MFP_LPM_EDGE_FALL,
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	/* AC97 */
110*4882a593Smuzhiyun 	GPIO23_AC97_nACRESET,
111*4882a593Smuzhiyun 	GPIO24_AC97_SYSCLK,
112*4882a593Smuzhiyun 	GPIO29_AC97_BITCLK,
113*4882a593Smuzhiyun 	GPIO25_AC97_SDATA_IN_0,
114*4882a593Smuzhiyun 	GPIO27_AC97_SDATA_OUT,
115*4882a593Smuzhiyun 	GPIO28_AC97_SYNC,
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* Keypad */
118*4882a593Smuzhiyun 	GPIO115_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
119*4882a593Smuzhiyun 	GPIO116_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
120*4882a593Smuzhiyun 	GPIO117_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
121*4882a593Smuzhiyun 	GPIO118_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
122*4882a593Smuzhiyun 	GPIO119_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
123*4882a593Smuzhiyun 	GPIO120_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
124*4882a593Smuzhiyun 	GPIO2_2_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
125*4882a593Smuzhiyun 	GPIO3_2_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
126*4882a593Smuzhiyun 	GPIO121_KP_MKOUT_0,
127*4882a593Smuzhiyun 	GPIO122_KP_MKOUT_1,
128*4882a593Smuzhiyun 	GPIO123_KP_MKOUT_2,
129*4882a593Smuzhiyun 	GPIO124_KP_MKOUT_3,
130*4882a593Smuzhiyun 	GPIO125_KP_MKOUT_4,
131*4882a593Smuzhiyun 	GPIO4_2_KP_MKOUT_5,
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	/* MMC1 */
134*4882a593Smuzhiyun 	GPIO3_MMC1_DAT0,
135*4882a593Smuzhiyun 	GPIO4_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
136*4882a593Smuzhiyun 	GPIO5_MMC1_DAT2,
137*4882a593Smuzhiyun 	GPIO6_MMC1_DAT3,
138*4882a593Smuzhiyun 	GPIO7_MMC1_CLK,
139*4882a593Smuzhiyun 	GPIO8_MMC1_CMD,	/* CMD0 for slot 0 */
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* MMC2 */
142*4882a593Smuzhiyun 	GPIO9_MMC2_DAT0,
143*4882a593Smuzhiyun 	GPIO10_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
144*4882a593Smuzhiyun 	GPIO11_MMC2_DAT2,
145*4882a593Smuzhiyun 	GPIO12_MMC2_DAT3,
146*4882a593Smuzhiyun 	GPIO13_MMC2_CLK,
147*4882a593Smuzhiyun 	GPIO14_MMC2_CMD,
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	/* FFUART */
150*4882a593Smuzhiyun 	GPIO30_UART1_RXD | MFP_LPM_EDGE_FALL,
151*4882a593Smuzhiyun 	GPIO31_UART1_TXD,
152*4882a593Smuzhiyun 	GPIO32_UART1_CTS,
153*4882a593Smuzhiyun 	GPIO37_UART1_RTS,
154*4882a593Smuzhiyun 	GPIO33_UART1_DCD,
155*4882a593Smuzhiyun 	GPIO34_UART1_DSR | MFP_LPM_EDGE_FALL,
156*4882a593Smuzhiyun 	GPIO35_UART1_RI,
157*4882a593Smuzhiyun 	GPIO36_UART1_DTR,
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	/* GPIOs */
160*4882a593Smuzhiyun 	GPIO82_GPIO | MFP_PULL_HIGH,	/* MMC CD */
161*4882a593Smuzhiyun 	GPIO85_GPIO,			/* MMC WP */
162*4882a593Smuzhiyun 	GPIO99_GPIO,			/* Ethernet IRQ */
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* RTC GPIOs */
165*4882a593Smuzhiyun 	GPIO95_GPIO | MFP_LPM_DRIVE_HIGH,	/* RTC CS */
166*4882a593Smuzhiyun 	GPIO96_GPIO | MFP_LPM_DRIVE_HIGH,	/* RTC WR */
167*4882a593Smuzhiyun 	GPIO97_GPIO | MFP_LPM_DRIVE_HIGH,	/* RTC RD */
168*4882a593Smuzhiyun 	GPIO98_GPIO,				/* RTC IO */
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	/* Standard I2C */
171*4882a593Smuzhiyun 	GPIO21_I2C_SCL,
172*4882a593Smuzhiyun 	GPIO22_I2C_SDA,
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	/* PWM Backlight */
175*4882a593Smuzhiyun 	GPIO19_PWM2_OUT,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun static mfp_cfg_t cm_x3xx_rev_lt130_mfp_cfg[] __initdata = {
179*4882a593Smuzhiyun 	/* GPIOs */
180*4882a593Smuzhiyun 	GPIO79_GPIO,			/* LED */
181*4882a593Smuzhiyun 	GPIO77_GPIO,			/* WiFi reset */
182*4882a593Smuzhiyun 	GPIO78_GPIO,			/* BT reset */
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun static mfp_cfg_t cm_x3xx_rev_ge130_mfp_cfg[] __initdata = {
186*4882a593Smuzhiyun 	/* GPIOs */
187*4882a593Smuzhiyun 	GPIO76_GPIO,			/* LED */
188*4882a593Smuzhiyun 	GPIO71_GPIO,			/* WiFi reset */
189*4882a593Smuzhiyun 	GPIO70_GPIO,			/* BT reset */
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun static mfp_cfg_t cm_x310_mfp_cfg[] __initdata = {
193*4882a593Smuzhiyun 	/* USB PORT 2 */
194*4882a593Smuzhiyun 	ULPI_STP,
195*4882a593Smuzhiyun 	ULPI_NXT,
196*4882a593Smuzhiyun 	ULPI_DIR,
197*4882a593Smuzhiyun 	GPIO30_ULPI_DATA_OUT_0,
198*4882a593Smuzhiyun 	GPIO31_ULPI_DATA_OUT_1,
199*4882a593Smuzhiyun 	GPIO32_ULPI_DATA_OUT_2,
200*4882a593Smuzhiyun 	GPIO33_ULPI_DATA_OUT_3,
201*4882a593Smuzhiyun 	GPIO34_ULPI_DATA_OUT_4,
202*4882a593Smuzhiyun 	GPIO35_ULPI_DATA_OUT_5,
203*4882a593Smuzhiyun 	GPIO36_ULPI_DATA_OUT_6,
204*4882a593Smuzhiyun 	GPIO37_ULPI_DATA_OUT_7,
205*4882a593Smuzhiyun 	GPIO38_ULPI_CLK,
206*4882a593Smuzhiyun 	/* external PHY reset pin */
207*4882a593Smuzhiyun 	GPIO127_GPIO,
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	/* USB PORT 3 */
210*4882a593Smuzhiyun 	GPIO77_USB_P3_1,
211*4882a593Smuzhiyun 	GPIO78_USB_P3_2,
212*4882a593Smuzhiyun 	GPIO79_USB_P3_3,
213*4882a593Smuzhiyun 	GPIO80_USB_P3_4,
214*4882a593Smuzhiyun 	GPIO81_USB_P3_5,
215*4882a593Smuzhiyun 	GPIO82_USB_P3_6,
216*4882a593Smuzhiyun 	GPIO0_2_USBH_PEN,
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
220*4882a593Smuzhiyun static struct resource dm9000_resources[] = {
221*4882a593Smuzhiyun 	[0] = {
222*4882a593Smuzhiyun 		.start	= CM_X300_ETH_PHYS,
223*4882a593Smuzhiyun 		.end	= CM_X300_ETH_PHYS + 0x3,
224*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
225*4882a593Smuzhiyun 	},
226*4882a593Smuzhiyun 	[1] = {
227*4882a593Smuzhiyun 		.start	= CM_X300_ETH_PHYS + 0x4,
228*4882a593Smuzhiyun 		.end	= CM_X300_ETH_PHYS + 0x4 + 500,
229*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
230*4882a593Smuzhiyun 	},
231*4882a593Smuzhiyun 	[2] = {
232*4882a593Smuzhiyun 		.start	= PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)),
233*4882a593Smuzhiyun 		.end	= PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)),
234*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
235*4882a593Smuzhiyun 	}
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun static struct dm9000_plat_data cm_x300_dm9000_platdata = {
239*4882a593Smuzhiyun 	.flags		= DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun static struct platform_device dm9000_device = {
243*4882a593Smuzhiyun 	.name		= "dm9000",
244*4882a593Smuzhiyun 	.id		= 0,
245*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(dm9000_resources),
246*4882a593Smuzhiyun 	.resource	= dm9000_resources,
247*4882a593Smuzhiyun 	.dev		= {
248*4882a593Smuzhiyun 		.platform_data = &cm_x300_dm9000_platdata,
249*4882a593Smuzhiyun 	}
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun 
cm_x300_init_dm9000(void)253*4882a593Smuzhiyun static void __init cm_x300_init_dm9000(void)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun 	platform_device_register(&dm9000_device);
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun #else
cm_x300_init_dm9000(void)258*4882a593Smuzhiyun static inline void cm_x300_init_dm9000(void) {}
259*4882a593Smuzhiyun #endif
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun /* LCD */
262*4882a593Smuzhiyun #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
263*4882a593Smuzhiyun static struct pxafb_mode_info cm_x300_lcd_modes[] = {
264*4882a593Smuzhiyun 	[0] = {
265*4882a593Smuzhiyun 		.pixclock	= 38250,
266*4882a593Smuzhiyun 		.bpp		= 16,
267*4882a593Smuzhiyun 		.xres		= 480,
268*4882a593Smuzhiyun 		.yres		= 640,
269*4882a593Smuzhiyun 		.hsync_len	= 8,
270*4882a593Smuzhiyun 		.vsync_len	= 2,
271*4882a593Smuzhiyun 		.left_margin	= 8,
272*4882a593Smuzhiyun 		.upper_margin	= 2,
273*4882a593Smuzhiyun 		.right_margin	= 24,
274*4882a593Smuzhiyun 		.lower_margin	= 4,
275*4882a593Smuzhiyun 		.cmap_greyscale	= 0,
276*4882a593Smuzhiyun 	},
277*4882a593Smuzhiyun 	[1] = {
278*4882a593Smuzhiyun 		.pixclock	= 153800,
279*4882a593Smuzhiyun 		.bpp		= 16,
280*4882a593Smuzhiyun 		.xres		= 240,
281*4882a593Smuzhiyun 		.yres		= 320,
282*4882a593Smuzhiyun 		.hsync_len	= 8,
283*4882a593Smuzhiyun 		.vsync_len	= 2,
284*4882a593Smuzhiyun 		.left_margin	= 8,
285*4882a593Smuzhiyun 		.upper_margin	= 2,
286*4882a593Smuzhiyun 		.right_margin	= 88,
287*4882a593Smuzhiyun 		.lower_margin	= 2,
288*4882a593Smuzhiyun 		.cmap_greyscale	= 0,
289*4882a593Smuzhiyun 	},
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static struct pxafb_mach_info cm_x300_lcd = {
293*4882a593Smuzhiyun 	.modes			= cm_x300_lcd_modes,
294*4882a593Smuzhiyun 	.num_modes		= ARRAY_SIZE(cm_x300_lcd_modes),
295*4882a593Smuzhiyun 	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun 
cm_x300_init_lcd(void)298*4882a593Smuzhiyun static void __init cm_x300_init_lcd(void)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	pxa_set_fb_info(NULL, &cm_x300_lcd);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun #else
cm_x300_init_lcd(void)303*4882a593Smuzhiyun static inline void cm_x300_init_lcd(void) {}
304*4882a593Smuzhiyun #endif
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun #if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
307*4882a593Smuzhiyun static struct pwm_lookup cm_x300_pwm_lookup[] = {
308*4882a593Smuzhiyun 	PWM_LOOKUP("pxa27x-pwm.0", 1, "pwm-backlight.0", NULL, 10000,
309*4882a593Smuzhiyun 		   PWM_POLARITY_NORMAL),
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun static struct platform_pwm_backlight_data cm_x300_backlight_data = {
313*4882a593Smuzhiyun 	.max_brightness	= 100,
314*4882a593Smuzhiyun 	.dft_brightness	= 100,
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun static struct platform_device cm_x300_backlight_device = {
318*4882a593Smuzhiyun 	.name		= "pwm-backlight",
319*4882a593Smuzhiyun 	.dev		= {
320*4882a593Smuzhiyun 		.parent = &pxa27x_device_pwm0.dev,
321*4882a593Smuzhiyun 		.platform_data	= &cm_x300_backlight_data,
322*4882a593Smuzhiyun 	},
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun 
cm_x300_init_bl(void)325*4882a593Smuzhiyun static void cm_x300_init_bl(void)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun 	pwm_add_table(cm_x300_pwm_lookup, ARRAY_SIZE(cm_x300_pwm_lookup));
328*4882a593Smuzhiyun 	platform_device_register(&cm_x300_backlight_device);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun #else
cm_x300_init_bl(void)331*4882a593Smuzhiyun static inline void cm_x300_init_bl(void) {}
332*4882a593Smuzhiyun #endif
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun #if defined(CONFIG_SPI_GPIO) || defined(CONFIG_SPI_GPIO_MODULE)
335*4882a593Smuzhiyun #define GPIO_LCD_BASE	(144)
336*4882a593Smuzhiyun #define GPIO_LCD_DIN	(GPIO_LCD_BASE + 8)	/* aux_gpio3_0 */
337*4882a593Smuzhiyun #define GPIO_LCD_DOUT	(GPIO_LCD_BASE + 9)	/* aux_gpio3_1 */
338*4882a593Smuzhiyun #define GPIO_LCD_SCL	(GPIO_LCD_BASE + 10)	/* aux_gpio3_2 */
339*4882a593Smuzhiyun #define GPIO_LCD_CS	(GPIO_LCD_BASE + 11)	/* aux_gpio3_3 */
340*4882a593Smuzhiyun #define LCD_SPI_BUS_NUM	(1)
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun static struct spi_gpio_platform_data cm_x300_spi_gpio_pdata = {
343*4882a593Smuzhiyun 	.num_chipselect	= 1,
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun static struct platform_device cm_x300_spi_gpio = {
347*4882a593Smuzhiyun 	.name		= "spi_gpio",
348*4882a593Smuzhiyun 	.id		= LCD_SPI_BUS_NUM,
349*4882a593Smuzhiyun 	.dev		= {
350*4882a593Smuzhiyun 		.platform_data	= &cm_x300_spi_gpio_pdata,
351*4882a593Smuzhiyun 	},
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun static struct gpiod_lookup_table cm_x300_spi_gpiod_table = {
355*4882a593Smuzhiyun 	.dev_id         = "spi_gpio",
356*4882a593Smuzhiyun 	.table          = {
357*4882a593Smuzhiyun 		GPIO_LOOKUP("pca9555.1", GPIO_LCD_SCL - GPIO_LCD_BASE,
358*4882a593Smuzhiyun 			    "sck", GPIO_ACTIVE_HIGH),
359*4882a593Smuzhiyun 		GPIO_LOOKUP("pca9555.1", GPIO_LCD_DIN - GPIO_LCD_BASE,
360*4882a593Smuzhiyun 			    "mosi", GPIO_ACTIVE_HIGH),
361*4882a593Smuzhiyun 		GPIO_LOOKUP("pca9555.1", GPIO_LCD_DOUT - GPIO_LCD_BASE,
362*4882a593Smuzhiyun 			    "miso", GPIO_ACTIVE_HIGH),
363*4882a593Smuzhiyun 		GPIO_LOOKUP("pca9555.1", GPIO_LCD_CS - GPIO_LCD_BASE,
364*4882a593Smuzhiyun 			    "cs", GPIO_ACTIVE_HIGH),
365*4882a593Smuzhiyun 		{ },
366*4882a593Smuzhiyun 	},
367*4882a593Smuzhiyun };
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun static struct tdo24m_platform_data cm_x300_tdo24m_pdata = {
370*4882a593Smuzhiyun 	.model = TDO35S,
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun static struct spi_board_info cm_x300_spi_devices[] __initdata = {
374*4882a593Smuzhiyun 	{
375*4882a593Smuzhiyun 		.modalias		= "tdo24m",
376*4882a593Smuzhiyun 		.max_speed_hz		= 1000000,
377*4882a593Smuzhiyun 		.bus_num		= LCD_SPI_BUS_NUM,
378*4882a593Smuzhiyun 		.chip_select		= 0,
379*4882a593Smuzhiyun 		.platform_data		= &cm_x300_tdo24m_pdata,
380*4882a593Smuzhiyun 	},
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun 
cm_x300_init_spi(void)383*4882a593Smuzhiyun static void __init cm_x300_init_spi(void)
384*4882a593Smuzhiyun {
385*4882a593Smuzhiyun 	spi_register_board_info(cm_x300_spi_devices,
386*4882a593Smuzhiyun 				ARRAY_SIZE(cm_x300_spi_devices));
387*4882a593Smuzhiyun 	gpiod_add_lookup_table(&cm_x300_spi_gpiod_table);
388*4882a593Smuzhiyun 	platform_device_register(&cm_x300_spi_gpio);
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun #else
cm_x300_init_spi(void)391*4882a593Smuzhiyun static inline void cm_x300_init_spi(void) {}
392*4882a593Smuzhiyun #endif
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun #if defined(CONFIG_SND_PXA2XX_LIB_AC97)
cm_x300_init_ac97(void)395*4882a593Smuzhiyun static void __init cm_x300_init_ac97(void)
396*4882a593Smuzhiyun {
397*4882a593Smuzhiyun 	pxa_set_ac97_info(NULL);
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun #else
cm_x300_init_ac97(void)400*4882a593Smuzhiyun static inline void cm_x300_init_ac97(void) {}
401*4882a593Smuzhiyun #endif
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
404*4882a593Smuzhiyun static struct mtd_partition cm_x300_nand_partitions[] = {
405*4882a593Smuzhiyun 	[0] = {
406*4882a593Smuzhiyun 		.name        = "OBM",
407*4882a593Smuzhiyun 		.offset      = 0,
408*4882a593Smuzhiyun 		.size        = SZ_256K,
409*4882a593Smuzhiyun 		.mask_flags  = MTD_WRITEABLE, /* force read-only */
410*4882a593Smuzhiyun 	},
411*4882a593Smuzhiyun 	[1] = {
412*4882a593Smuzhiyun 		.name        = "U-Boot",
413*4882a593Smuzhiyun 		.offset      = MTDPART_OFS_APPEND,
414*4882a593Smuzhiyun 		.size        = SZ_256K,
415*4882a593Smuzhiyun 		.mask_flags  = MTD_WRITEABLE, /* force read-only */
416*4882a593Smuzhiyun 	},
417*4882a593Smuzhiyun 	[2] = {
418*4882a593Smuzhiyun 		.name        = "Environment",
419*4882a593Smuzhiyun 		.offset      = MTDPART_OFS_APPEND,
420*4882a593Smuzhiyun 		.size        = SZ_256K,
421*4882a593Smuzhiyun 	},
422*4882a593Smuzhiyun 	[3] = {
423*4882a593Smuzhiyun 		.name        = "reserved",
424*4882a593Smuzhiyun 		.offset      = MTDPART_OFS_APPEND,
425*4882a593Smuzhiyun 		.size        = SZ_256K + SZ_1M,
426*4882a593Smuzhiyun 		.mask_flags  = MTD_WRITEABLE, /* force read-only */
427*4882a593Smuzhiyun 	},
428*4882a593Smuzhiyun 	[4] = {
429*4882a593Smuzhiyun 		.name        = "kernel",
430*4882a593Smuzhiyun 		.offset      = MTDPART_OFS_APPEND,
431*4882a593Smuzhiyun 		.size        = SZ_4M,
432*4882a593Smuzhiyun 	},
433*4882a593Smuzhiyun 	[5] = {
434*4882a593Smuzhiyun 		.name        = "fs",
435*4882a593Smuzhiyun 		.offset      = MTDPART_OFS_APPEND,
436*4882a593Smuzhiyun 		.size        = MTDPART_SIZ_FULL,
437*4882a593Smuzhiyun 	},
438*4882a593Smuzhiyun };
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
441*4882a593Smuzhiyun 	.keep_config	= 1,
442*4882a593Smuzhiyun 	.parts		= cm_x300_nand_partitions,
443*4882a593Smuzhiyun 	.nr_parts	= ARRAY_SIZE(cm_x300_nand_partitions),
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun 
cm_x300_init_nand(void)446*4882a593Smuzhiyun static void __init cm_x300_init_nand(void)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	pxa3xx_set_nand_info(&cm_x300_nand_info);
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun #else
cm_x300_init_nand(void)451*4882a593Smuzhiyun static inline void cm_x300_init_nand(void) {}
452*4882a593Smuzhiyun #endif
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
455*4882a593Smuzhiyun static struct pxamci_platform_data cm_x300_mci_platform_data = {
456*4882a593Smuzhiyun 	.detect_delay_ms	= 200,
457*4882a593Smuzhiyun 	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
458*4882a593Smuzhiyun };
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun static struct gpiod_lookup_table cm_x300_mci_gpio_table = {
461*4882a593Smuzhiyun 	.dev_id = "pxa2xx-mci.0",
462*4882a593Smuzhiyun 	.table = {
463*4882a593Smuzhiyun 		/* Card detect on GPIO 82 */
464*4882a593Smuzhiyun 		GPIO_LOOKUP("gpio-pxa", GPIO82_MMC_IRQ, "cd", GPIO_ACTIVE_LOW),
465*4882a593Smuzhiyun 		/* Write protect on GPIO 85 */
466*4882a593Smuzhiyun 		GPIO_LOOKUP("gpio-pxa", GPIO85_MMC_WP, "wp", GPIO_ACTIVE_LOW),
467*4882a593Smuzhiyun 		{ },
468*4882a593Smuzhiyun 	},
469*4882a593Smuzhiyun };
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun /* The second MMC slot of CM-X300 is hardwired to Libertas card and has
472*4882a593Smuzhiyun    no detection/ro pins */
cm_x300_mci2_init(struct device * dev,irq_handler_t cm_x300_detect_int,void * data)473*4882a593Smuzhiyun static int cm_x300_mci2_init(struct device *dev,
474*4882a593Smuzhiyun 			     irq_handler_t cm_x300_detect_int,
475*4882a593Smuzhiyun 	void *data)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun 	return 0;
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun 
cm_x300_mci2_exit(struct device * dev,void * data)480*4882a593Smuzhiyun static void cm_x300_mci2_exit(struct device *dev, void *data)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun static struct pxamci_platform_data cm_x300_mci2_platform_data = {
485*4882a593Smuzhiyun 	.detect_delay_ms	= 200,
486*4882a593Smuzhiyun 	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
487*4882a593Smuzhiyun 	.init 			= cm_x300_mci2_init,
488*4882a593Smuzhiyun 	.exit			= cm_x300_mci2_exit,
489*4882a593Smuzhiyun };
490*4882a593Smuzhiyun 
cm_x300_init_mmc(void)491*4882a593Smuzhiyun static void __init cm_x300_init_mmc(void)
492*4882a593Smuzhiyun {
493*4882a593Smuzhiyun 	gpiod_add_lookup_table(&cm_x300_mci_gpio_table);
494*4882a593Smuzhiyun 	pxa_set_mci_info(&cm_x300_mci_platform_data);
495*4882a593Smuzhiyun 	pxa3xx_set_mci2_info(&cm_x300_mci2_platform_data);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun #else
cm_x300_init_mmc(void)498*4882a593Smuzhiyun static inline void cm_x300_init_mmc(void) {}
499*4882a593Smuzhiyun #endif
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun #if defined(CONFIG_PXA310_ULPI)
502*4882a593Smuzhiyun static struct clk *pout_clk;
503*4882a593Smuzhiyun 
cm_x300_ulpi_phy_reset(void)504*4882a593Smuzhiyun static int cm_x300_ulpi_phy_reset(void)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun 	int err;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	/* reset the PHY */
509*4882a593Smuzhiyun 	err = gpio_request_one(GPIO_ULPI_PHY_RST, GPIOF_OUT_INIT_LOW,
510*4882a593Smuzhiyun 			       "ulpi reset");
511*4882a593Smuzhiyun 	if (err) {
512*4882a593Smuzhiyun 		pr_err("failed to request ULPI reset GPIO: %d\n", err);
513*4882a593Smuzhiyun 		return err;
514*4882a593Smuzhiyun 	}
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	msleep(10);
517*4882a593Smuzhiyun 	gpio_set_value(GPIO_ULPI_PHY_RST, 1);
518*4882a593Smuzhiyun 	msleep(10);
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	gpio_free(GPIO_ULPI_PHY_RST);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun 
cm_x300_u2d_init(struct device * dev)525*4882a593Smuzhiyun static int cm_x300_u2d_init(struct device *dev)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun 	int err = 0;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	if (cpu_is_pxa310()) {
530*4882a593Smuzhiyun 		/* CLK_POUT is connected to the ULPI PHY */
531*4882a593Smuzhiyun 		pout_clk = clk_get(NULL, "CLK_POUT");
532*4882a593Smuzhiyun 		if (IS_ERR(pout_clk)) {
533*4882a593Smuzhiyun 			err = PTR_ERR(pout_clk);
534*4882a593Smuzhiyun 			pr_err("failed to get CLK_POUT: %d\n", err);
535*4882a593Smuzhiyun 			return err;
536*4882a593Smuzhiyun 		}
537*4882a593Smuzhiyun 		clk_prepare_enable(pout_clk);
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 		err = cm_x300_ulpi_phy_reset();
540*4882a593Smuzhiyun 		if (err) {
541*4882a593Smuzhiyun 			clk_disable(pout_clk);
542*4882a593Smuzhiyun 			clk_put(pout_clk);
543*4882a593Smuzhiyun 		}
544*4882a593Smuzhiyun 	}
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	return err;
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun 
cm_x300_u2d_exit(struct device * dev)549*4882a593Smuzhiyun static void cm_x300_u2d_exit(struct device *dev)
550*4882a593Smuzhiyun {
551*4882a593Smuzhiyun 	if (cpu_is_pxa310()) {
552*4882a593Smuzhiyun 		clk_disable_unprepare(pout_clk);
553*4882a593Smuzhiyun 		clk_put(pout_clk);
554*4882a593Smuzhiyun 	}
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun static struct pxa3xx_u2d_platform_data cm_x300_u2d_platform_data = {
558*4882a593Smuzhiyun 	.ulpi_mode	= ULPI_SER_6PIN,
559*4882a593Smuzhiyun 	.init		= cm_x300_u2d_init,
560*4882a593Smuzhiyun 	.exit		= cm_x300_u2d_exit,
561*4882a593Smuzhiyun };
562*4882a593Smuzhiyun 
cm_x300_init_u2d(void)563*4882a593Smuzhiyun static void __init cm_x300_init_u2d(void)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun 	pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data);
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun #else
cm_x300_init_u2d(void)568*4882a593Smuzhiyun static inline void cm_x300_init_u2d(void) {}
569*4882a593Smuzhiyun #endif
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
cm_x300_ohci_init(struct device * dev)572*4882a593Smuzhiyun static int cm_x300_ohci_init(struct device *dev)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun 	if (cpu_is_pxa300())
575*4882a593Smuzhiyun 		UP2OCR = UP2OCR_HXS
576*4882a593Smuzhiyun 			| UP2OCR_HXOE | UP2OCR_DMPDE | UP2OCR_DPPDE;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	return 0;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun static struct pxaohci_platform_data cm_x300_ohci_platform_data = {
582*4882a593Smuzhiyun 	.port_mode	= PMM_PERPORT_MODE,
583*4882a593Smuzhiyun 	.flags		= ENABLE_PORT_ALL | POWER_CONTROL_LOW,
584*4882a593Smuzhiyun 	.init		= cm_x300_ohci_init,
585*4882a593Smuzhiyun };
586*4882a593Smuzhiyun 
cm_x300_init_ohci(void)587*4882a593Smuzhiyun static void __init cm_x300_init_ohci(void)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun 	pxa_set_ohci_info(&cm_x300_ohci_platform_data);
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun #else
cm_x300_init_ohci(void)592*4882a593Smuzhiyun static inline void cm_x300_init_ohci(void) {}
593*4882a593Smuzhiyun #endif
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
596*4882a593Smuzhiyun static struct gpio_led cm_x300_leds[] = {
597*4882a593Smuzhiyun 	[0] = {
598*4882a593Smuzhiyun 		.name = "cm-x300:green",
599*4882a593Smuzhiyun 		.default_trigger = "heartbeat",
600*4882a593Smuzhiyun 		.active_low = 1,
601*4882a593Smuzhiyun 	},
602*4882a593Smuzhiyun };
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun static struct gpio_led_platform_data cm_x300_gpio_led_pdata = {
605*4882a593Smuzhiyun 	.num_leds = ARRAY_SIZE(cm_x300_leds),
606*4882a593Smuzhiyun 	.leds = cm_x300_leds,
607*4882a593Smuzhiyun };
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun static struct platform_device cm_x300_led_device = {
610*4882a593Smuzhiyun 	.name		= "leds-gpio",
611*4882a593Smuzhiyun 	.id		= -1,
612*4882a593Smuzhiyun 	.dev		= {
613*4882a593Smuzhiyun 		.platform_data = &cm_x300_gpio_led_pdata,
614*4882a593Smuzhiyun 	},
615*4882a593Smuzhiyun };
616*4882a593Smuzhiyun 
cm_x300_init_leds(void)617*4882a593Smuzhiyun static void __init cm_x300_init_leds(void)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun 	if (system_rev < 130)
620*4882a593Smuzhiyun 		cm_x300_leds[0].gpio = 79;
621*4882a593Smuzhiyun 	else
622*4882a593Smuzhiyun 		cm_x300_leds[0].gpio = 76;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	platform_device_register(&cm_x300_led_device);
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun #else
cm_x300_init_leds(void)627*4882a593Smuzhiyun static inline void cm_x300_init_leds(void) {}
628*4882a593Smuzhiyun #endif
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
631*4882a593Smuzhiyun /* PCA9555 */
632*4882a593Smuzhiyun static struct pca953x_platform_data cm_x300_gpio_ext_pdata_0 = {
633*4882a593Smuzhiyun 	.gpio_base = 128,
634*4882a593Smuzhiyun };
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun static struct pca953x_platform_data cm_x300_gpio_ext_pdata_1 = {
637*4882a593Smuzhiyun 	.gpio_base = 144,
638*4882a593Smuzhiyun };
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun static struct i2c_board_info cm_x300_gpio_ext_info[] = {
641*4882a593Smuzhiyun 	[0] = {
642*4882a593Smuzhiyun 		I2C_BOARD_INFO("pca9555", 0x24),
643*4882a593Smuzhiyun 		.platform_data = &cm_x300_gpio_ext_pdata_0,
644*4882a593Smuzhiyun 	},
645*4882a593Smuzhiyun 	[1] = {
646*4882a593Smuzhiyun 		I2C_BOARD_INFO("pca9555", 0x25),
647*4882a593Smuzhiyun 		.platform_data = &cm_x300_gpio_ext_pdata_1,
648*4882a593Smuzhiyun 	},
649*4882a593Smuzhiyun };
650*4882a593Smuzhiyun 
cm_x300_init_i2c(void)651*4882a593Smuzhiyun static void __init cm_x300_init_i2c(void)
652*4882a593Smuzhiyun {
653*4882a593Smuzhiyun 	pxa_set_i2c_info(NULL);
654*4882a593Smuzhiyun 	i2c_register_board_info(0, cm_x300_gpio_ext_info,
655*4882a593Smuzhiyun 				ARRAY_SIZE(cm_x300_gpio_ext_info));
656*4882a593Smuzhiyun }
657*4882a593Smuzhiyun #else
cm_x300_init_i2c(void)658*4882a593Smuzhiyun static inline void cm_x300_init_i2c(void) {}
659*4882a593Smuzhiyun #endif
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun #if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
662*4882a593Smuzhiyun struct v3020_platform_data cm_x300_v3020_pdata = {
663*4882a593Smuzhiyun 	.use_gpio	= 1,
664*4882a593Smuzhiyun 	.gpio_cs	= GPIO95_RTC_CS,
665*4882a593Smuzhiyun 	.gpio_wr	= GPIO96_RTC_WR,
666*4882a593Smuzhiyun 	.gpio_rd	= GPIO97_RTC_RD,
667*4882a593Smuzhiyun 	.gpio_io	= GPIO98_RTC_IO,
668*4882a593Smuzhiyun };
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun static struct platform_device cm_x300_rtc_device = {
671*4882a593Smuzhiyun 	.name		= "v3020",
672*4882a593Smuzhiyun 	.id		= -1,
673*4882a593Smuzhiyun 	.dev		= {
674*4882a593Smuzhiyun 		.platform_data = &cm_x300_v3020_pdata,
675*4882a593Smuzhiyun 	}
676*4882a593Smuzhiyun };
677*4882a593Smuzhiyun 
cm_x300_init_rtc(void)678*4882a593Smuzhiyun static void __init cm_x300_init_rtc(void)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun 	platform_device_register(&cm_x300_rtc_device);
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun #else
cm_x300_init_rtc(void)683*4882a593Smuzhiyun static inline void cm_x300_init_rtc(void) {}
684*4882a593Smuzhiyun #endif
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun /* Battery */
687*4882a593Smuzhiyun struct power_supply_info cm_x300_psy_info = {
688*4882a593Smuzhiyun 	.name = "battery",
689*4882a593Smuzhiyun 	.technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
690*4882a593Smuzhiyun 	.voltage_max_design = 4200000,
691*4882a593Smuzhiyun 	.voltage_min_design = 3000000,
692*4882a593Smuzhiyun 	.use_for_apm = 1,
693*4882a593Smuzhiyun };
694*4882a593Smuzhiyun 
cm_x300_battery_low(void)695*4882a593Smuzhiyun static void cm_x300_battery_low(void)
696*4882a593Smuzhiyun {
697*4882a593Smuzhiyun #if defined(CONFIG_APM_EMULATION)
698*4882a593Smuzhiyun 	apm_queue_event(APM_LOW_BATTERY);
699*4882a593Smuzhiyun #endif
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun 
cm_x300_battery_critical(void)702*4882a593Smuzhiyun static void cm_x300_battery_critical(void)
703*4882a593Smuzhiyun {
704*4882a593Smuzhiyun #if defined(CONFIG_APM_EMULATION)
705*4882a593Smuzhiyun 	apm_queue_event(APM_CRITICAL_SUSPEND);
706*4882a593Smuzhiyun #endif
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun struct da9030_battery_info cm_x300_battery_info = {
710*4882a593Smuzhiyun 	.battery_info = &cm_x300_psy_info,
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 	.charge_milliamp = 1000,
713*4882a593Smuzhiyun 	.charge_millivolt = 4200,
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	.vbat_low = 3600,
716*4882a593Smuzhiyun 	.vbat_crit = 3400,
717*4882a593Smuzhiyun 	.vbat_charge_start = 4100,
718*4882a593Smuzhiyun 	.vbat_charge_stop = 4200,
719*4882a593Smuzhiyun 	.vbat_charge_restart = 4000,
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	.vcharge_min = 3200,
722*4882a593Smuzhiyun 	.vcharge_max = 5500,
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	.tbat_low = 197,
725*4882a593Smuzhiyun 	.tbat_high = 78,
726*4882a593Smuzhiyun 	.tbat_restart = 100,
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	.batmon_interval = 0,
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun 	.battery_low = cm_x300_battery_low,
731*4882a593Smuzhiyun 	.battery_critical = cm_x300_battery_critical,
732*4882a593Smuzhiyun };
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun static struct regulator_consumer_supply buck2_consumers[] = {
735*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vcc_core", NULL),
736*4882a593Smuzhiyun };
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun static struct regulator_init_data buck2_data = {
739*4882a593Smuzhiyun 	.constraints = {
740*4882a593Smuzhiyun 		.min_uV = 1375000,
741*4882a593Smuzhiyun 		.max_uV = 1375000,
742*4882a593Smuzhiyun 		.state_mem = {
743*4882a593Smuzhiyun 			.enabled = 0,
744*4882a593Smuzhiyun 		},
745*4882a593Smuzhiyun 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
746*4882a593Smuzhiyun 		.apply_uV = 1,
747*4882a593Smuzhiyun 	},
748*4882a593Smuzhiyun 	.num_consumer_supplies = ARRAY_SIZE(buck2_consumers),
749*4882a593Smuzhiyun 	.consumer_supplies = buck2_consumers,
750*4882a593Smuzhiyun };
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun /* DA9030 */
753*4882a593Smuzhiyun struct da903x_subdev_info cm_x300_da9030_subdevs[] = {
754*4882a593Smuzhiyun 	{
755*4882a593Smuzhiyun 		.name = "da903x-battery",
756*4882a593Smuzhiyun 		.id = DA9030_ID_BAT,
757*4882a593Smuzhiyun 		.platform_data = &cm_x300_battery_info,
758*4882a593Smuzhiyun 	},
759*4882a593Smuzhiyun 	{
760*4882a593Smuzhiyun 		.name = "da903x-regulator",
761*4882a593Smuzhiyun 		.id = DA9030_ID_BUCK2,
762*4882a593Smuzhiyun 		.platform_data = &buck2_data,
763*4882a593Smuzhiyun 	},
764*4882a593Smuzhiyun };
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun static struct da903x_platform_data cm_x300_da9030_info = {
767*4882a593Smuzhiyun 	.num_subdevs = ARRAY_SIZE(cm_x300_da9030_subdevs),
768*4882a593Smuzhiyun 	.subdevs = cm_x300_da9030_subdevs,
769*4882a593Smuzhiyun };
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun static struct i2c_board_info cm_x300_pmic_info = {
772*4882a593Smuzhiyun 	I2C_BOARD_INFO("da9030", 0x49),
773*4882a593Smuzhiyun 	.irq = IRQ_WAKEUP0,
774*4882a593Smuzhiyun 	.platform_data = &cm_x300_da9030_info,
775*4882a593Smuzhiyun };
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun static struct i2c_pxa_platform_data cm_x300_pwr_i2c_info = {
778*4882a593Smuzhiyun 	.use_pio = 1,
779*4882a593Smuzhiyun };
780*4882a593Smuzhiyun 
cm_x300_init_da9030(void)781*4882a593Smuzhiyun static void __init cm_x300_init_da9030(void)
782*4882a593Smuzhiyun {
783*4882a593Smuzhiyun 	pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
784*4882a593Smuzhiyun 	i2c_register_board_info(1, &cm_x300_pmic_info, 1);
785*4882a593Smuzhiyun 	irq_set_irq_wake(IRQ_WAKEUP0, 1);
786*4882a593Smuzhiyun }
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun /* wi2wi gpio setting for system_rev >= 130 */
789*4882a593Smuzhiyun static struct gpio cm_x300_wi2wi_gpios[] __initdata = {
790*4882a593Smuzhiyun 	{ 71, GPIOF_OUT_INIT_HIGH, "wlan en" },
791*4882a593Smuzhiyun 	{ 70, GPIOF_OUT_INIT_HIGH, "bt reset" },
792*4882a593Smuzhiyun };
793*4882a593Smuzhiyun 
cm_x300_init_wi2wi(void)794*4882a593Smuzhiyun static void __init cm_x300_init_wi2wi(void)
795*4882a593Smuzhiyun {
796*4882a593Smuzhiyun 	int err;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 	if (system_rev < 130) {
799*4882a593Smuzhiyun 		cm_x300_wi2wi_gpios[0].gpio = 77;	/* wlan en */
800*4882a593Smuzhiyun 		cm_x300_wi2wi_gpios[1].gpio = 78;	/* bt reset */
801*4882a593Smuzhiyun 	}
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 	/* Libertas and CSR reset */
804*4882a593Smuzhiyun 	err = gpio_request_array(ARRAY_AND_SIZE(cm_x300_wi2wi_gpios));
805*4882a593Smuzhiyun 	if (err) {
806*4882a593Smuzhiyun 		pr_err("failed to request wifi/bt gpios: %d\n", err);
807*4882a593Smuzhiyun 		return;
808*4882a593Smuzhiyun 	}
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	udelay(10);
811*4882a593Smuzhiyun 	gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 0);
812*4882a593Smuzhiyun 	udelay(10);
813*4882a593Smuzhiyun 	gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 1);
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 	gpio_free_array(ARRAY_AND_SIZE(cm_x300_wi2wi_gpios));
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun 
818*4882a593Smuzhiyun /* MFP */
cm_x300_init_mfp(void)819*4882a593Smuzhiyun static void __init cm_x300_init_mfp(void)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun 	/* board-processor specific GPIO initialization */
822*4882a593Smuzhiyun 	pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_mfp_cfg));
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun 	if (system_rev < 130)
825*4882a593Smuzhiyun 		pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_lt130_mfp_cfg));
826*4882a593Smuzhiyun 	else
827*4882a593Smuzhiyun 		pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_ge130_mfp_cfg));
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun 	if (cpu_is_pxa310())
830*4882a593Smuzhiyun 		pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x310_mfp_cfg));
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun 
cm_x300_init(void)833*4882a593Smuzhiyun static void __init cm_x300_init(void)
834*4882a593Smuzhiyun {
835*4882a593Smuzhiyun 	cm_x300_init_mfp();
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 	pxa_set_btuart_info(NULL);
838*4882a593Smuzhiyun 	pxa_set_stuart_info(NULL);
839*4882a593Smuzhiyun 	if (cpu_is_pxa300())
840*4882a593Smuzhiyun 		pxa_set_ffuart_info(NULL);
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 	cm_x300_init_da9030();
843*4882a593Smuzhiyun 	cm_x300_init_dm9000();
844*4882a593Smuzhiyun 	cm_x300_init_lcd();
845*4882a593Smuzhiyun 	cm_x300_init_u2d();
846*4882a593Smuzhiyun 	cm_x300_init_ohci();
847*4882a593Smuzhiyun 	cm_x300_init_mmc();
848*4882a593Smuzhiyun 	cm_x300_init_nand();
849*4882a593Smuzhiyun 	cm_x300_init_leds();
850*4882a593Smuzhiyun 	cm_x300_init_i2c();
851*4882a593Smuzhiyun 	cm_x300_init_spi();
852*4882a593Smuzhiyun 	cm_x300_init_rtc();
853*4882a593Smuzhiyun 	cm_x300_init_ac97();
854*4882a593Smuzhiyun 	cm_x300_init_wi2wi();
855*4882a593Smuzhiyun 	cm_x300_init_bl();
856*4882a593Smuzhiyun 
857*4882a593Smuzhiyun 	regulator_has_full_constraints();
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun 
cm_x300_fixup(struct tag * tags,char ** cmdline)860*4882a593Smuzhiyun static void __init cm_x300_fixup(struct tag *tags, char **cmdline)
861*4882a593Smuzhiyun {
862*4882a593Smuzhiyun 	/* Make sure that mi->bank[0].start = PHYS_ADDR */
863*4882a593Smuzhiyun 	for (; tags->hdr.size; tags = tag_next(tags))
864*4882a593Smuzhiyun 		if (tags->hdr.tag == ATAG_MEM &&
865*4882a593Smuzhiyun 			tags->u.mem.start == 0x80000000) {
866*4882a593Smuzhiyun 			tags->u.mem.start = 0xa0000000;
867*4882a593Smuzhiyun 			break;
868*4882a593Smuzhiyun 		}
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun MACHINE_START(CM_X300, "CM-X300 module")
872*4882a593Smuzhiyun 	.atag_offset	= 0x100,
873*4882a593Smuzhiyun 	.map_io		= pxa3xx_map_io,
874*4882a593Smuzhiyun 	.nr_irqs	= PXA_NR_IRQS,
875*4882a593Smuzhiyun 	.init_irq	= pxa3xx_init_irq,
876*4882a593Smuzhiyun 	.handle_irq	= pxa3xx_handle_irq,
877*4882a593Smuzhiyun 	.init_time	= pxa_timer_init,
878*4882a593Smuzhiyun 	.init_machine	= cm_x300_init,
879*4882a593Smuzhiyun 	.fixup		= cm_x300_fixup,
880*4882a593Smuzhiyun 	.restart	= pxa_restart,
881*4882a593Smuzhiyun MACHINE_END
882