xref: /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/balloon3.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  linux/arch/arm/mach-pxa/balloon3.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Support for Balloonboard.org Balloon3 board.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *  Author:	Nick Bane, Wookey, Jonathan McDowell
8*4882a593Smuzhiyun  *  Created:	June, 2006
9*4882a593Smuzhiyun  *  Copyright:	Toby Churchill Ltd
10*4882a593Smuzhiyun  *  Derived from mainstone.c, by Nico Pitre
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/export.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/leds.h>
18*4882a593Smuzhiyun #include <linux/sched.h>
19*4882a593Smuzhiyun #include <linux/bitops.h>
20*4882a593Smuzhiyun #include <linux/fb.h>
21*4882a593Smuzhiyun #include <linux/gpio.h>
22*4882a593Smuzhiyun #include <linux/ioport.h>
23*4882a593Smuzhiyun #include <linux/ucb1400.h>
24*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
25*4882a593Smuzhiyun #include <linux/types.h>
26*4882a593Smuzhiyun #include <linux/platform_data/pcf857x.h>
27*4882a593Smuzhiyun #include <linux/platform_data/i2c-pxa.h>
28*4882a593Smuzhiyun #include <linux/mtd/platnand.h>
29*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
30*4882a593Smuzhiyun #include <linux/regulator/max1586.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #include <asm/setup.h>
33*4882a593Smuzhiyun #include <asm/mach-types.h>
34*4882a593Smuzhiyun #include <asm/irq.h>
35*4882a593Smuzhiyun #include <linux/sizes.h>
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #include <asm/mach/arch.h>
38*4882a593Smuzhiyun #include <asm/mach/map.h>
39*4882a593Smuzhiyun #include <asm/mach/irq.h>
40*4882a593Smuzhiyun #include <asm/mach/flash.h>
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #include "pxa27x.h"
43*4882a593Smuzhiyun #include <mach/balloon3.h>
44*4882a593Smuzhiyun #include <mach/audio.h>
45*4882a593Smuzhiyun #include <linux/platform_data/video-pxafb.h>
46*4882a593Smuzhiyun #include <linux/platform_data/mmc-pxamci.h>
47*4882a593Smuzhiyun #include "udc.h"
48*4882a593Smuzhiyun #include "pxa27x-udc.h"
49*4882a593Smuzhiyun #include <linux/platform_data/irda-pxaficp.h>
50*4882a593Smuzhiyun #include <linux/platform_data/usb-ohci-pxa27x.h>
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #include "generic.h"
53*4882a593Smuzhiyun #include "devices.h"
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /******************************************************************************
56*4882a593Smuzhiyun  * Pin configuration
57*4882a593Smuzhiyun  ******************************************************************************/
58*4882a593Smuzhiyun static unsigned long balloon3_pin_config[] __initdata = {
59*4882a593Smuzhiyun 	/* Select BTUART 'COM1/ttyS0' as IO option for pins 42/43/44/45 */
60*4882a593Smuzhiyun 	GPIO42_BTUART_RXD,
61*4882a593Smuzhiyun 	GPIO43_BTUART_TXD,
62*4882a593Smuzhiyun 	GPIO44_BTUART_CTS,
63*4882a593Smuzhiyun 	GPIO45_BTUART_RTS,
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	/* Reset, configured as GPIO wakeup source */
66*4882a593Smuzhiyun 	GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /******************************************************************************
70*4882a593Smuzhiyun  * Compatibility: Parameter parsing
71*4882a593Smuzhiyun  ******************************************************************************/
72*4882a593Smuzhiyun static unsigned long balloon3_irq_enabled;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun static unsigned long balloon3_features_present =
75*4882a593Smuzhiyun 		(1 << BALLOON3_FEATURE_OHCI) | (1 << BALLOON3_FEATURE_CF) |
76*4882a593Smuzhiyun 		(1 << BALLOON3_FEATURE_AUDIO) |
77*4882a593Smuzhiyun 		(1 << BALLOON3_FEATURE_TOPPOLY);
78*4882a593Smuzhiyun 
balloon3_has(enum balloon3_features feature)79*4882a593Smuzhiyun int balloon3_has(enum balloon3_features feature)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	return (balloon3_features_present & (1 << feature)) ? 1 : 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(balloon3_has);
84*4882a593Smuzhiyun 
parse_balloon3_features(char * arg)85*4882a593Smuzhiyun int __init parse_balloon3_features(char *arg)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	if (!arg)
88*4882a593Smuzhiyun 		return 0;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	return kstrtoul(arg, 0, &balloon3_features_present);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun early_param("balloon3_features", parse_balloon3_features);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /******************************************************************************
95*4882a593Smuzhiyun  * Compact Flash slot
96*4882a593Smuzhiyun  ******************************************************************************/
97*4882a593Smuzhiyun #if	defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
98*4882a593Smuzhiyun static unsigned long balloon3_cf_pin_config[] __initdata = {
99*4882a593Smuzhiyun 	GPIO48_nPOE,
100*4882a593Smuzhiyun 	GPIO49_nPWE,
101*4882a593Smuzhiyun 	GPIO50_nPIOR,
102*4882a593Smuzhiyun 	GPIO51_nPIOW,
103*4882a593Smuzhiyun 	GPIO85_nPCE_1,
104*4882a593Smuzhiyun 	GPIO54_nPCE_2,
105*4882a593Smuzhiyun 	GPIO79_PSKTSEL,
106*4882a593Smuzhiyun 	GPIO55_nPREG,
107*4882a593Smuzhiyun 	GPIO56_nPWAIT,
108*4882a593Smuzhiyun 	GPIO57_nIOIS16,
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun 
balloon3_cf_init(void)111*4882a593Smuzhiyun static void __init balloon3_cf_init(void)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	if (!balloon3_has(BALLOON3_FEATURE_CF))
114*4882a593Smuzhiyun 		return;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_cf_pin_config));
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun #else
balloon3_cf_init(void)119*4882a593Smuzhiyun static inline void balloon3_cf_init(void) {}
120*4882a593Smuzhiyun #endif
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /******************************************************************************
123*4882a593Smuzhiyun  * NOR Flash
124*4882a593Smuzhiyun  ******************************************************************************/
125*4882a593Smuzhiyun #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
126*4882a593Smuzhiyun static struct mtd_partition balloon3_nor_partitions[] = {
127*4882a593Smuzhiyun 	{
128*4882a593Smuzhiyun 		.name		= "Flash",
129*4882a593Smuzhiyun 		.offset		= 0x00000000,
130*4882a593Smuzhiyun 		.size		= MTDPART_SIZ_FULL,
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun static struct physmap_flash_data balloon3_flash_data[] = {
135*4882a593Smuzhiyun 	{
136*4882a593Smuzhiyun 		.width		= 2,	/* bankwidth in bytes */
137*4882a593Smuzhiyun 		.parts		= balloon3_nor_partitions,
138*4882a593Smuzhiyun 		.nr_parts	= ARRAY_SIZE(balloon3_nor_partitions)
139*4882a593Smuzhiyun 	}
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun static struct resource balloon3_flash_resource = {
143*4882a593Smuzhiyun 	.start	= PXA_CS0_PHYS,
144*4882a593Smuzhiyun 	.end	= PXA_CS0_PHYS + SZ_64M - 1,
145*4882a593Smuzhiyun 	.flags	= IORESOURCE_MEM,
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static struct platform_device balloon3_flash = {
149*4882a593Smuzhiyun 	.name		= "physmap-flash",
150*4882a593Smuzhiyun 	.id		= 0,
151*4882a593Smuzhiyun 	.resource	= &balloon3_flash_resource,
152*4882a593Smuzhiyun 	.num_resources	= 1,
153*4882a593Smuzhiyun 	.dev 		= {
154*4882a593Smuzhiyun 		.platform_data = balloon3_flash_data,
155*4882a593Smuzhiyun 	},
156*4882a593Smuzhiyun };
balloon3_nor_init(void)157*4882a593Smuzhiyun static void __init balloon3_nor_init(void)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	platform_device_register(&balloon3_flash);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun #else
balloon3_nor_init(void)162*4882a593Smuzhiyun static inline void balloon3_nor_init(void) {}
163*4882a593Smuzhiyun #endif
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /******************************************************************************
166*4882a593Smuzhiyun  * Audio and Touchscreen
167*4882a593Smuzhiyun  ******************************************************************************/
168*4882a593Smuzhiyun #if	defined(CONFIG_TOUCHSCREEN_UCB1400) || \
169*4882a593Smuzhiyun 	defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
170*4882a593Smuzhiyun static unsigned long balloon3_ac97_pin_config[] __initdata = {
171*4882a593Smuzhiyun 	GPIO28_AC97_BITCLK,
172*4882a593Smuzhiyun 	GPIO29_AC97_SDATA_IN_0,
173*4882a593Smuzhiyun 	GPIO30_AC97_SDATA_OUT,
174*4882a593Smuzhiyun 	GPIO31_AC97_SYNC,
175*4882a593Smuzhiyun 	GPIO113_AC97_nRESET,
176*4882a593Smuzhiyun 	GPIO95_GPIO,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun static struct ucb1400_pdata vpac270_ucb1400_pdata = {
180*4882a593Smuzhiyun 	.irq		= PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ),
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun static struct platform_device balloon3_ucb1400_device = {
185*4882a593Smuzhiyun 	.name		= "ucb1400_core",
186*4882a593Smuzhiyun 	.id		= -1,
187*4882a593Smuzhiyun 	.dev		= {
188*4882a593Smuzhiyun 		.platform_data = &vpac270_ucb1400_pdata,
189*4882a593Smuzhiyun 	},
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
balloon3_ts_init(void)192*4882a593Smuzhiyun static void __init balloon3_ts_init(void)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	if (!balloon3_has(BALLOON3_FEATURE_AUDIO))
195*4882a593Smuzhiyun 		return;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ac97_pin_config));
198*4882a593Smuzhiyun 	pxa_set_ac97_info(NULL);
199*4882a593Smuzhiyun 	platform_device_register(&balloon3_ucb1400_device);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun #else
balloon3_ts_init(void)202*4882a593Smuzhiyun static inline void balloon3_ts_init(void) {}
203*4882a593Smuzhiyun #endif
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun /******************************************************************************
206*4882a593Smuzhiyun  * Framebuffer
207*4882a593Smuzhiyun  ******************************************************************************/
208*4882a593Smuzhiyun #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
209*4882a593Smuzhiyun static unsigned long balloon3_lcd_pin_config[] __initdata = {
210*4882a593Smuzhiyun 	GPIOxx_LCD_TFT_16BPP,
211*4882a593Smuzhiyun 	GPIO99_GPIO,
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun static struct pxafb_mode_info balloon3_lcd_modes[] = {
215*4882a593Smuzhiyun 	{
216*4882a593Smuzhiyun 		.pixclock		= 38000,
217*4882a593Smuzhiyun 		.xres			= 480,
218*4882a593Smuzhiyun 		.yres			= 640,
219*4882a593Smuzhiyun 		.bpp			= 16,
220*4882a593Smuzhiyun 		.hsync_len		= 8,
221*4882a593Smuzhiyun 		.left_margin		= 8,
222*4882a593Smuzhiyun 		.right_margin		= 8,
223*4882a593Smuzhiyun 		.vsync_len		= 2,
224*4882a593Smuzhiyun 		.upper_margin		= 4,
225*4882a593Smuzhiyun 		.lower_margin		= 5,
226*4882a593Smuzhiyun 		.sync			= 0,
227*4882a593Smuzhiyun 	},
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun static struct pxafb_mach_info balloon3_lcd_screen = {
231*4882a593Smuzhiyun 	.modes			= balloon3_lcd_modes,
232*4882a593Smuzhiyun 	.num_modes		= ARRAY_SIZE(balloon3_lcd_modes),
233*4882a593Smuzhiyun 	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun 
balloon3_backlight_power(int on)236*4882a593Smuzhiyun static void balloon3_backlight_power(int on)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	gpio_set_value(BALLOON3_GPIO_RUN_BACKLIGHT, on);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
balloon3_lcd_init(void)241*4882a593Smuzhiyun static void __init balloon3_lcd_init(void)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	int ret;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	if (!balloon3_has(BALLOON3_FEATURE_TOPPOLY))
246*4882a593Smuzhiyun 		return;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config));
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	ret = gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, "BKL-ON");
251*4882a593Smuzhiyun 	if (ret) {
252*4882a593Smuzhiyun 		pr_err("Requesting BKL-ON GPIO failed!\n");
253*4882a593Smuzhiyun 		goto err;
254*4882a593Smuzhiyun 	}
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	ret = gpio_direction_output(BALLOON3_GPIO_RUN_BACKLIGHT, 1);
257*4882a593Smuzhiyun 	if (ret) {
258*4882a593Smuzhiyun 		pr_err("Setting BKL-ON GPIO direction failed!\n");
259*4882a593Smuzhiyun 		goto err2;
260*4882a593Smuzhiyun 	}
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power;
263*4882a593Smuzhiyun 	pxa_set_fb_info(NULL, &balloon3_lcd_screen);
264*4882a593Smuzhiyun 	return;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun err2:
267*4882a593Smuzhiyun 	gpio_free(BALLOON3_GPIO_RUN_BACKLIGHT);
268*4882a593Smuzhiyun err:
269*4882a593Smuzhiyun 	return;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun #else
balloon3_lcd_init(void)272*4882a593Smuzhiyun static inline void balloon3_lcd_init(void) {}
273*4882a593Smuzhiyun #endif
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun /******************************************************************************
276*4882a593Smuzhiyun  * SD/MMC card controller
277*4882a593Smuzhiyun  ******************************************************************************/
278*4882a593Smuzhiyun #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
279*4882a593Smuzhiyun static unsigned long balloon3_mmc_pin_config[] __initdata = {
280*4882a593Smuzhiyun 	GPIO32_MMC_CLK,
281*4882a593Smuzhiyun 	GPIO92_MMC_DAT_0,
282*4882a593Smuzhiyun 	GPIO109_MMC_DAT_1,
283*4882a593Smuzhiyun 	GPIO110_MMC_DAT_2,
284*4882a593Smuzhiyun 	GPIO111_MMC_DAT_3,
285*4882a593Smuzhiyun 	GPIO112_MMC_CMD,
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun static struct pxamci_platform_data balloon3_mci_platform_data = {
289*4882a593Smuzhiyun 	.ocr_mask		= MMC_VDD_32_33 | MMC_VDD_33_34,
290*4882a593Smuzhiyun 	.detect_delay_ms	= 200,
291*4882a593Smuzhiyun };
292*4882a593Smuzhiyun 
balloon3_mmc_init(void)293*4882a593Smuzhiyun static void __init balloon3_mmc_init(void)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_mmc_pin_config));
296*4882a593Smuzhiyun 	pxa_set_mci_info(&balloon3_mci_platform_data);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun #else
balloon3_mmc_init(void)299*4882a593Smuzhiyun static inline void balloon3_mmc_init(void) {}
300*4882a593Smuzhiyun #endif
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun /******************************************************************************
303*4882a593Smuzhiyun  * USB Gadget
304*4882a593Smuzhiyun  ******************************************************************************/
305*4882a593Smuzhiyun #if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
balloon3_udc_command(int cmd)306*4882a593Smuzhiyun static void balloon3_udc_command(int cmd)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun 	if (cmd == PXA2XX_UDC_CMD_CONNECT)
309*4882a593Smuzhiyun 		UP2OCR |= UP2OCR_DPPUE | UP2OCR_DPPUBE;
310*4882a593Smuzhiyun 	else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
311*4882a593Smuzhiyun 		UP2OCR &= ~UP2OCR_DPPUE;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
balloon3_udc_is_connected(void)314*4882a593Smuzhiyun static int balloon3_udc_is_connected(void)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun 	return 1;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun static struct pxa2xx_udc_mach_info balloon3_udc_info __initdata = {
320*4882a593Smuzhiyun 	.udc_command		= balloon3_udc_command,
321*4882a593Smuzhiyun 	.udc_is_connected	= balloon3_udc_is_connected,
322*4882a593Smuzhiyun 	.gpio_pullup		= -1,
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun 
balloon3_udc_init(void)325*4882a593Smuzhiyun static void __init balloon3_udc_init(void)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun 	pxa_set_udc_info(&balloon3_udc_info);
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun #else
balloon3_udc_init(void)330*4882a593Smuzhiyun static inline void balloon3_udc_init(void) {}
331*4882a593Smuzhiyun #endif
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun /******************************************************************************
334*4882a593Smuzhiyun  * IrDA
335*4882a593Smuzhiyun  ******************************************************************************/
336*4882a593Smuzhiyun #if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE)
337*4882a593Smuzhiyun static struct pxaficp_platform_data balloon3_ficp_platform_data = {
338*4882a593Smuzhiyun 	.transceiver_cap	= IR_FIRMODE | IR_SIRMODE | IR_OFF,
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun 
balloon3_irda_init(void)341*4882a593Smuzhiyun static void __init balloon3_irda_init(void)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun 	pxa_set_ficp_info(&balloon3_ficp_platform_data);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun #else
balloon3_irda_init(void)346*4882a593Smuzhiyun static inline void balloon3_irda_init(void) {}
347*4882a593Smuzhiyun #endif
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun /******************************************************************************
350*4882a593Smuzhiyun  * USB Host
351*4882a593Smuzhiyun  ******************************************************************************/
352*4882a593Smuzhiyun #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
353*4882a593Smuzhiyun static unsigned long balloon3_uhc_pin_config[] __initdata = {
354*4882a593Smuzhiyun 	GPIO88_USBH1_PWR,
355*4882a593Smuzhiyun 	GPIO89_USBH1_PEN,
356*4882a593Smuzhiyun };
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun static struct pxaohci_platform_data balloon3_ohci_info = {
359*4882a593Smuzhiyun 	.port_mode	= PMM_PERPORT_MODE,
360*4882a593Smuzhiyun 	.flags		= ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
balloon3_uhc_init(void)363*4882a593Smuzhiyun static void __init balloon3_uhc_init(void)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun 	if (!balloon3_has(BALLOON3_FEATURE_OHCI))
366*4882a593Smuzhiyun 		return;
367*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_uhc_pin_config));
368*4882a593Smuzhiyun 	pxa_set_ohci_info(&balloon3_ohci_info);
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun #else
balloon3_uhc_init(void)371*4882a593Smuzhiyun static inline void balloon3_uhc_init(void) {}
372*4882a593Smuzhiyun #endif
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun /******************************************************************************
375*4882a593Smuzhiyun  * LEDs
376*4882a593Smuzhiyun  ******************************************************************************/
377*4882a593Smuzhiyun #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
378*4882a593Smuzhiyun static unsigned long balloon3_led_pin_config[] __initdata = {
379*4882a593Smuzhiyun 	GPIO9_GPIO,	/* NAND activity LED */
380*4882a593Smuzhiyun 	GPIO10_GPIO,	/* Heartbeat LED */
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun struct gpio_led balloon3_gpio_leds[] = {
384*4882a593Smuzhiyun 	{
385*4882a593Smuzhiyun 		.name			= "balloon3:green:idle",
386*4882a593Smuzhiyun 		.default_trigger	= "heartbeat",
387*4882a593Smuzhiyun 		.gpio			= BALLOON3_GPIO_LED_IDLE,
388*4882a593Smuzhiyun 		.active_low		= 1,
389*4882a593Smuzhiyun 	}, {
390*4882a593Smuzhiyun 		.name			= "balloon3:green:nand",
391*4882a593Smuzhiyun 		.default_trigger	= "nand-disk",
392*4882a593Smuzhiyun 		.gpio			= BALLOON3_GPIO_LED_NAND,
393*4882a593Smuzhiyun 		.active_low		= 1,
394*4882a593Smuzhiyun 	},
395*4882a593Smuzhiyun };
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun static struct gpio_led_platform_data balloon3_gpio_led_info = {
398*4882a593Smuzhiyun 	.leds		= balloon3_gpio_leds,
399*4882a593Smuzhiyun 	.num_leds	= ARRAY_SIZE(balloon3_gpio_leds),
400*4882a593Smuzhiyun };
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun static struct platform_device balloon3_leds = {
403*4882a593Smuzhiyun 	.name	= "leds-gpio",
404*4882a593Smuzhiyun 	.id	= 0,
405*4882a593Smuzhiyun 	.dev	= {
406*4882a593Smuzhiyun 		.platform_data	= &balloon3_gpio_led_info,
407*4882a593Smuzhiyun 	}
408*4882a593Smuzhiyun };
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun struct gpio_led balloon3_pcf_gpio_leds[] = {
411*4882a593Smuzhiyun 	{
412*4882a593Smuzhiyun 		.name			= "balloon3:green:led0",
413*4882a593Smuzhiyun 		.gpio			= BALLOON3_PCF_GPIO_LED0,
414*4882a593Smuzhiyun 		.active_low		= 1,
415*4882a593Smuzhiyun 	}, {
416*4882a593Smuzhiyun 		.name			= "balloon3:green:led1",
417*4882a593Smuzhiyun 		.gpio			= BALLOON3_PCF_GPIO_LED1,
418*4882a593Smuzhiyun 		.active_low		= 1,
419*4882a593Smuzhiyun 	}, {
420*4882a593Smuzhiyun 		.name			= "balloon3:orange:led2",
421*4882a593Smuzhiyun 		.gpio			= BALLOON3_PCF_GPIO_LED2,
422*4882a593Smuzhiyun 		.active_low		= 1,
423*4882a593Smuzhiyun 	}, {
424*4882a593Smuzhiyun 		.name			= "balloon3:orange:led3",
425*4882a593Smuzhiyun 		.gpio			= BALLOON3_PCF_GPIO_LED3,
426*4882a593Smuzhiyun 		.active_low		= 1,
427*4882a593Smuzhiyun 	}, {
428*4882a593Smuzhiyun 		.name			= "balloon3:orange:led4",
429*4882a593Smuzhiyun 		.gpio			= BALLOON3_PCF_GPIO_LED4,
430*4882a593Smuzhiyun 		.active_low		= 1,
431*4882a593Smuzhiyun 	}, {
432*4882a593Smuzhiyun 		.name			= "balloon3:orange:led5",
433*4882a593Smuzhiyun 		.gpio			= BALLOON3_PCF_GPIO_LED5,
434*4882a593Smuzhiyun 		.active_low		= 1,
435*4882a593Smuzhiyun 	}, {
436*4882a593Smuzhiyun 		.name			= "balloon3:red:led6",
437*4882a593Smuzhiyun 		.gpio			= BALLOON3_PCF_GPIO_LED6,
438*4882a593Smuzhiyun 		.active_low		= 1,
439*4882a593Smuzhiyun 	}, {
440*4882a593Smuzhiyun 		.name			= "balloon3:red:led7",
441*4882a593Smuzhiyun 		.gpio			= BALLOON3_PCF_GPIO_LED7,
442*4882a593Smuzhiyun 		.active_low		= 1,
443*4882a593Smuzhiyun 	},
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun static struct gpio_led_platform_data balloon3_pcf_gpio_led_info = {
447*4882a593Smuzhiyun 	.leds		= balloon3_pcf_gpio_leds,
448*4882a593Smuzhiyun 	.num_leds	= ARRAY_SIZE(balloon3_pcf_gpio_leds),
449*4882a593Smuzhiyun };
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun static struct platform_device balloon3_pcf_leds = {
452*4882a593Smuzhiyun 	.name	= "leds-gpio",
453*4882a593Smuzhiyun 	.id	= 1,
454*4882a593Smuzhiyun 	.dev	= {
455*4882a593Smuzhiyun 		.platform_data	= &balloon3_pcf_gpio_led_info,
456*4882a593Smuzhiyun 	}
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun 
balloon3_leds_init(void)459*4882a593Smuzhiyun static void __init balloon3_leds_init(void)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_led_pin_config));
462*4882a593Smuzhiyun 	platform_device_register(&balloon3_leds);
463*4882a593Smuzhiyun 	platform_device_register(&balloon3_pcf_leds);
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun #else
balloon3_leds_init(void)466*4882a593Smuzhiyun static inline void balloon3_leds_init(void) {}
467*4882a593Smuzhiyun #endif
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun /******************************************************************************
470*4882a593Smuzhiyun  * FPGA IRQ
471*4882a593Smuzhiyun  ******************************************************************************/
balloon3_mask_irq(struct irq_data * d)472*4882a593Smuzhiyun static void balloon3_mask_irq(struct irq_data *d)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun 	int balloon3_irq = (d->irq - BALLOON3_IRQ(0));
475*4882a593Smuzhiyun 	balloon3_irq_enabled &= ~(1 << balloon3_irq);
476*4882a593Smuzhiyun 	__raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun 
balloon3_unmask_irq(struct irq_data * d)479*4882a593Smuzhiyun static void balloon3_unmask_irq(struct irq_data *d)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun 	int balloon3_irq = (d->irq - BALLOON3_IRQ(0));
482*4882a593Smuzhiyun 	balloon3_irq_enabled |= (1 << balloon3_irq);
483*4882a593Smuzhiyun 	__raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun static struct irq_chip balloon3_irq_chip = {
487*4882a593Smuzhiyun 	.name		= "FPGA",
488*4882a593Smuzhiyun 	.irq_ack	= balloon3_mask_irq,
489*4882a593Smuzhiyun 	.irq_mask	= balloon3_mask_irq,
490*4882a593Smuzhiyun 	.irq_unmask	= balloon3_unmask_irq,
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun 
balloon3_irq_handler(struct irq_desc * desc)493*4882a593Smuzhiyun static void balloon3_irq_handler(struct irq_desc *desc)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun 	unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
496*4882a593Smuzhiyun 					balloon3_irq_enabled;
497*4882a593Smuzhiyun 	do {
498*4882a593Smuzhiyun 		struct irq_data *d = irq_desc_get_irq_data(desc);
499*4882a593Smuzhiyun 		struct irq_chip *chip = irq_desc_get_chip(desc);
500*4882a593Smuzhiyun 		unsigned int irq;
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 		/* clear useless edge notification */
503*4882a593Smuzhiyun 		if (chip->irq_ack)
504*4882a593Smuzhiyun 			chip->irq_ack(d);
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 		while (pending) {
507*4882a593Smuzhiyun 			irq = BALLOON3_IRQ(0) + __ffs(pending);
508*4882a593Smuzhiyun 			generic_handle_irq(irq);
509*4882a593Smuzhiyun 			pending &= pending - 1;
510*4882a593Smuzhiyun 		}
511*4882a593Smuzhiyun 		pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
512*4882a593Smuzhiyun 				balloon3_irq_enabled;
513*4882a593Smuzhiyun 	} while (pending);
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun 
balloon3_init_irq(void)516*4882a593Smuzhiyun static void __init balloon3_init_irq(void)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun 	int irq;
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	pxa27x_init_irq();
521*4882a593Smuzhiyun 	/* setup extra Balloon3 irqs */
522*4882a593Smuzhiyun 	for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
523*4882a593Smuzhiyun 		irq_set_chip_and_handler(irq, &balloon3_irq_chip,
524*4882a593Smuzhiyun 					 handle_level_irq);
525*4882a593Smuzhiyun 		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
526*4882a593Smuzhiyun 	}
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
529*4882a593Smuzhiyun 	irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	pr_debug("%s: chained handler installed - irq %d automatically "
532*4882a593Smuzhiyun 		"enabled\n", __func__, BALLOON3_AUX_NIRQ);
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun /******************************************************************************
536*4882a593Smuzhiyun  * GPIO expander
537*4882a593Smuzhiyun  ******************************************************************************/
538*4882a593Smuzhiyun #if defined(CONFIG_GPIO_PCF857X) || defined(CONFIG_GPIO_PCF857X_MODULE)
539*4882a593Smuzhiyun static struct pcf857x_platform_data balloon3_pcf857x_pdata = {
540*4882a593Smuzhiyun 	.gpio_base	= BALLOON3_PCF_GPIO_BASE,
541*4882a593Smuzhiyun 	.n_latch	= 0,
542*4882a593Smuzhiyun 	.setup		= NULL,
543*4882a593Smuzhiyun 	.teardown	= NULL,
544*4882a593Smuzhiyun 	.context	= NULL,
545*4882a593Smuzhiyun };
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun static struct i2c_board_info __initdata balloon3_i2c_devs[] = {
548*4882a593Smuzhiyun 	{
549*4882a593Smuzhiyun 		I2C_BOARD_INFO("pcf8574a", 0x38),
550*4882a593Smuzhiyun 		.platform_data	= &balloon3_pcf857x_pdata,
551*4882a593Smuzhiyun 	},
552*4882a593Smuzhiyun };
553*4882a593Smuzhiyun 
balloon3_i2c_init(void)554*4882a593Smuzhiyun static void __init balloon3_i2c_init(void)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun 	pxa_set_i2c_info(NULL);
557*4882a593Smuzhiyun 	i2c_register_board_info(0, ARRAY_AND_SIZE(balloon3_i2c_devs));
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun #else
balloon3_i2c_init(void)560*4882a593Smuzhiyun static inline void balloon3_i2c_init(void) {}
561*4882a593Smuzhiyun #endif
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun /******************************************************************************
564*4882a593Smuzhiyun  * NAND
565*4882a593Smuzhiyun  ******************************************************************************/
566*4882a593Smuzhiyun #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
balloon3_nand_cmd_ctl(struct nand_chip * this,int cmd,unsigned int ctrl)567*4882a593Smuzhiyun static void balloon3_nand_cmd_ctl(struct nand_chip *this, int cmd,
568*4882a593Smuzhiyun 				  unsigned int ctrl)
569*4882a593Smuzhiyun {
570*4882a593Smuzhiyun 	uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	if (ctrl & NAND_CTRL_CHANGE) {
573*4882a593Smuzhiyun 		if (ctrl & NAND_CLE)
574*4882a593Smuzhiyun 			balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE;
575*4882a593Smuzhiyun 		else
576*4882a593Smuzhiyun 			balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 		if (ctrl & NAND_ALE)
579*4882a593Smuzhiyun 			balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE;
580*4882a593Smuzhiyun 		else
581*4882a593Smuzhiyun 			balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE;
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 		if (balloon3_ctl_clr)
584*4882a593Smuzhiyun 			__raw_writel(balloon3_ctl_clr,
585*4882a593Smuzhiyun 				BALLOON3_NAND_CONTROL_REG);
586*4882a593Smuzhiyun 		if (balloon3_ctl_set)
587*4882a593Smuzhiyun 			__raw_writel(balloon3_ctl_set,
588*4882a593Smuzhiyun 				BALLOON3_NAND_CONTROL_REG +
589*4882a593Smuzhiyun 				BALLOON3_FPGA_SETnCLR);
590*4882a593Smuzhiyun 	}
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	if (cmd != NAND_CMD_NONE)
593*4882a593Smuzhiyun 		writeb(cmd, this->legacy.IO_ADDR_W);
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun 
balloon3_nand_select_chip(struct nand_chip * this,int chip)596*4882a593Smuzhiyun static void balloon3_nand_select_chip(struct nand_chip *this, int chip)
597*4882a593Smuzhiyun {
598*4882a593Smuzhiyun 	if (chip < 0 || chip > 3)
599*4882a593Smuzhiyun 		return;
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	/* Assert all nCE lines */
602*4882a593Smuzhiyun 	__raw_writew(
603*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
604*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3,
605*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR);
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	/* Deassert correct nCE line */
608*4882a593Smuzhiyun 	__raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip,
609*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL_REG);
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun 
balloon3_nand_dev_ready(struct nand_chip * this)612*4882a593Smuzhiyun static int balloon3_nand_dev_ready(struct nand_chip *this)
613*4882a593Smuzhiyun {
614*4882a593Smuzhiyun 	return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB;
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun 
balloon3_nand_probe(struct platform_device * pdev)617*4882a593Smuzhiyun static int balloon3_nand_probe(struct platform_device *pdev)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun 	uint16_t ver;
620*4882a593Smuzhiyun 	int ret;
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun 	__raw_writew(BALLOON3_NAND_CONTROL2_16BIT,
623*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL2_REG + BALLOON3_FPGA_SETnCLR);
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	ver = __raw_readw(BALLOON3_FPGA_VER);
626*4882a593Smuzhiyun 	if (ver < 0x4f08)
627*4882a593Smuzhiyun 		pr_warn("The FPGA code, version 0x%04x, is too old. "
628*4882a593Smuzhiyun 			"NAND support might be broken in this version!", ver);
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	/* Power up the NAND chips */
631*4882a593Smuzhiyun 	ret = gpio_request(BALLOON3_GPIO_RUN_NAND, "NAND");
632*4882a593Smuzhiyun 	if (ret)
633*4882a593Smuzhiyun 		goto err1;
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	ret = gpio_direction_output(BALLOON3_GPIO_RUN_NAND, 1);
636*4882a593Smuzhiyun 	if (ret)
637*4882a593Smuzhiyun 		goto err2;
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	/* Deassert all nCE lines and write protect line */
642*4882a593Smuzhiyun 	__raw_writel(
643*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
644*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
645*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL_FLWP,
646*4882a593Smuzhiyun 		BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR);
647*4882a593Smuzhiyun 	return 0;
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun err2:
650*4882a593Smuzhiyun 	gpio_free(BALLOON3_GPIO_RUN_NAND);
651*4882a593Smuzhiyun err1:
652*4882a593Smuzhiyun 	return ret;
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun 
balloon3_nand_remove(struct platform_device * pdev)655*4882a593Smuzhiyun static void balloon3_nand_remove(struct platform_device *pdev)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun 	/* Power down the NAND chips */
658*4882a593Smuzhiyun 	gpio_set_value(BALLOON3_GPIO_RUN_NAND, 0);
659*4882a593Smuzhiyun 	gpio_free(BALLOON3_GPIO_RUN_NAND);
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun static struct mtd_partition balloon3_partition_info[] = {
663*4882a593Smuzhiyun 	[0] = {
664*4882a593Smuzhiyun 		.name	= "Boot",
665*4882a593Smuzhiyun 		.offset	= 0,
666*4882a593Smuzhiyun 		.size	= SZ_4M,
667*4882a593Smuzhiyun 	},
668*4882a593Smuzhiyun 	[1] = {
669*4882a593Smuzhiyun 		.name	= "RootFS",
670*4882a593Smuzhiyun 		.offset	= MTDPART_OFS_APPEND,
671*4882a593Smuzhiyun 		.size	= MTDPART_SIZ_FULL
672*4882a593Smuzhiyun 	},
673*4882a593Smuzhiyun };
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun struct platform_nand_data balloon3_nand_pdata = {
676*4882a593Smuzhiyun 	.chip = {
677*4882a593Smuzhiyun 		.nr_chips	= 4,
678*4882a593Smuzhiyun 		.chip_offset	= 0,
679*4882a593Smuzhiyun 		.nr_partitions	= ARRAY_SIZE(balloon3_partition_info),
680*4882a593Smuzhiyun 		.partitions	= balloon3_partition_info,
681*4882a593Smuzhiyun 		.chip_delay	= 50,
682*4882a593Smuzhiyun 	},
683*4882a593Smuzhiyun 	.ctrl = {
684*4882a593Smuzhiyun 		.dev_ready	= balloon3_nand_dev_ready,
685*4882a593Smuzhiyun 		.select_chip	= balloon3_nand_select_chip,
686*4882a593Smuzhiyun 		.cmd_ctrl	= balloon3_nand_cmd_ctl,
687*4882a593Smuzhiyun 		.probe		= balloon3_nand_probe,
688*4882a593Smuzhiyun 		.remove		= balloon3_nand_remove,
689*4882a593Smuzhiyun 	},
690*4882a593Smuzhiyun };
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun static struct resource balloon3_nand_resource[] = {
693*4882a593Smuzhiyun 	[0] = {
694*4882a593Smuzhiyun 		.start = BALLOON3_NAND_BASE,
695*4882a593Smuzhiyun 		.end   = BALLOON3_NAND_BASE + 0x4,
696*4882a593Smuzhiyun 		.flags = IORESOURCE_MEM,
697*4882a593Smuzhiyun 	},
698*4882a593Smuzhiyun };
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun static struct platform_device balloon3_nand = {
701*4882a593Smuzhiyun 	.name		= "gen_nand",
702*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(balloon3_nand_resource),
703*4882a593Smuzhiyun 	.resource	= balloon3_nand_resource,
704*4882a593Smuzhiyun 	.id		= -1,
705*4882a593Smuzhiyun 	.dev		= {
706*4882a593Smuzhiyun 		.platform_data = &balloon3_nand_pdata,
707*4882a593Smuzhiyun 	}
708*4882a593Smuzhiyun };
709*4882a593Smuzhiyun 
balloon3_nand_init(void)710*4882a593Smuzhiyun static void __init balloon3_nand_init(void)
711*4882a593Smuzhiyun {
712*4882a593Smuzhiyun 	platform_device_register(&balloon3_nand);
713*4882a593Smuzhiyun }
714*4882a593Smuzhiyun #else
balloon3_nand_init(void)715*4882a593Smuzhiyun static inline void balloon3_nand_init(void) {}
716*4882a593Smuzhiyun #endif
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun /******************************************************************************
719*4882a593Smuzhiyun  * Core power regulator
720*4882a593Smuzhiyun  ******************************************************************************/
721*4882a593Smuzhiyun #if defined(CONFIG_REGULATOR_MAX1586) || \
722*4882a593Smuzhiyun     defined(CONFIG_REGULATOR_MAX1586_MODULE)
723*4882a593Smuzhiyun static struct regulator_consumer_supply balloon3_max1587a_consumers[] = {
724*4882a593Smuzhiyun 	REGULATOR_SUPPLY("vcc_core", NULL),
725*4882a593Smuzhiyun };
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun static struct regulator_init_data balloon3_max1587a_v3_info = {
728*4882a593Smuzhiyun 	.constraints = {
729*4882a593Smuzhiyun 		.name		= "vcc_core range",
730*4882a593Smuzhiyun 		.min_uV		= 900000,
731*4882a593Smuzhiyun 		.max_uV		= 1705000,
732*4882a593Smuzhiyun 		.always_on	= 1,
733*4882a593Smuzhiyun 		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
734*4882a593Smuzhiyun 	},
735*4882a593Smuzhiyun 	.consumer_supplies	= balloon3_max1587a_consumers,
736*4882a593Smuzhiyun 	.num_consumer_supplies	= ARRAY_SIZE(balloon3_max1587a_consumers),
737*4882a593Smuzhiyun };
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun static struct max1586_subdev_data balloon3_max1587a_subdevs[] = {
740*4882a593Smuzhiyun 	{
741*4882a593Smuzhiyun 		.name		= "vcc_core",
742*4882a593Smuzhiyun 		.id		= MAX1586_V3,
743*4882a593Smuzhiyun 		.platform_data	= &balloon3_max1587a_v3_info,
744*4882a593Smuzhiyun 	}
745*4882a593Smuzhiyun };
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun static struct max1586_platform_data balloon3_max1587a_info = {
748*4882a593Smuzhiyun 	.subdevs     = balloon3_max1587a_subdevs,
749*4882a593Smuzhiyun 	.num_subdevs = ARRAY_SIZE(balloon3_max1587a_subdevs),
750*4882a593Smuzhiyun 	.v3_gain     = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
751*4882a593Smuzhiyun };
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun static struct i2c_board_info __initdata balloon3_pi2c_board_info[] = {
754*4882a593Smuzhiyun 	{
755*4882a593Smuzhiyun 		I2C_BOARD_INFO("max1586", 0x14),
756*4882a593Smuzhiyun 		.platform_data	= &balloon3_max1587a_info,
757*4882a593Smuzhiyun 	},
758*4882a593Smuzhiyun };
759*4882a593Smuzhiyun 
balloon3_pmic_init(void)760*4882a593Smuzhiyun static void __init balloon3_pmic_init(void)
761*4882a593Smuzhiyun {
762*4882a593Smuzhiyun 	pxa27x_set_i2c_power_info(NULL);
763*4882a593Smuzhiyun 	i2c_register_board_info(1, ARRAY_AND_SIZE(balloon3_pi2c_board_info));
764*4882a593Smuzhiyun }
765*4882a593Smuzhiyun #else
balloon3_pmic_init(void)766*4882a593Smuzhiyun static inline void balloon3_pmic_init(void) {}
767*4882a593Smuzhiyun #endif
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun /******************************************************************************
770*4882a593Smuzhiyun  * Machine init
771*4882a593Smuzhiyun  ******************************************************************************/
balloon3_init(void)772*4882a593Smuzhiyun static void __init balloon3_init(void)
773*4882a593Smuzhiyun {
774*4882a593Smuzhiyun 	ARB_CNTRL = ARB_CORE_PARK | 0x234;
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun 	pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_pin_config));
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun 	pxa_set_ffuart_info(NULL);
779*4882a593Smuzhiyun 	pxa_set_btuart_info(NULL);
780*4882a593Smuzhiyun 	pxa_set_stuart_info(NULL);
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun 	balloon3_i2c_init();
783*4882a593Smuzhiyun 	balloon3_irda_init();
784*4882a593Smuzhiyun 	balloon3_lcd_init();
785*4882a593Smuzhiyun 	balloon3_leds_init();
786*4882a593Smuzhiyun 	balloon3_mmc_init();
787*4882a593Smuzhiyun 	balloon3_nand_init();
788*4882a593Smuzhiyun 	balloon3_nor_init();
789*4882a593Smuzhiyun 	balloon3_pmic_init();
790*4882a593Smuzhiyun 	balloon3_ts_init();
791*4882a593Smuzhiyun 	balloon3_udc_init();
792*4882a593Smuzhiyun 	balloon3_uhc_init();
793*4882a593Smuzhiyun 	balloon3_cf_init();
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun static struct map_desc balloon3_io_desc[] __initdata = {
797*4882a593Smuzhiyun 	{	/* CPLD/FPGA */
798*4882a593Smuzhiyun 		.virtual	= (unsigned long)BALLOON3_FPGA_VIRT,
799*4882a593Smuzhiyun 		.pfn		= __phys_to_pfn(BALLOON3_FPGA_PHYS),
800*4882a593Smuzhiyun 		.length		= BALLOON3_FPGA_LENGTH,
801*4882a593Smuzhiyun 		.type		= MT_DEVICE,
802*4882a593Smuzhiyun 	},
803*4882a593Smuzhiyun };
804*4882a593Smuzhiyun 
balloon3_map_io(void)805*4882a593Smuzhiyun static void __init balloon3_map_io(void)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun 	pxa27x_map_io();
808*4882a593Smuzhiyun 	iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc));
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun MACHINE_START(BALLOON3, "Balloon3")
812*4882a593Smuzhiyun 	/* Maintainer: Nick Bane. */
813*4882a593Smuzhiyun 	.map_io		= balloon3_map_io,
814*4882a593Smuzhiyun 	.nr_irqs	= BALLOON3_NR_IRQS,
815*4882a593Smuzhiyun 	.init_irq	= balloon3_init_irq,
816*4882a593Smuzhiyun 	.handle_irq	= pxa27x_handle_irq,
817*4882a593Smuzhiyun 	.init_time	= pxa_timer_init,
818*4882a593Smuzhiyun 	.init_machine	= balloon3_init,
819*4882a593Smuzhiyun 	.atag_offset	= 0x100,
820*4882a593Smuzhiyun 	.restart	= pxa_restart,
821*4882a593Smuzhiyun MACHINE_END
822