1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * sleep mode for CSR SiRFprimaII 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <linux/linkage.h> 9*4882a593Smuzhiyun#include <asm/ptrace.h> 10*4882a593Smuzhiyun#include <asm/assembler.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include "pm.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#define DENALI_CTL_22_OFF 0x58 15*4882a593Smuzhiyun#define DENALI_CTL_112_OFF 0x1c0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun .text 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunENTRY(sirfsoc_finish_suspend) 20*4882a593Smuzhiyun @ r5: mem controller 21*4882a593Smuzhiyun ldr r0, =sirfsoc_memc_base 22*4882a593Smuzhiyun ldr r5, [r0] 23*4882a593Smuzhiyun @ r6: pwrc base offset 24*4882a593Smuzhiyun ldr r0, =sirfsoc_pwrc_base 25*4882a593Smuzhiyun ldr r6, [r0] 26*4882a593Smuzhiyun @ r7: rtc iobrg controller 27*4882a593Smuzhiyun ldr r0, =sirfsoc_rtciobrg_base 28*4882a593Smuzhiyun ldr r7, [r0] 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun @ Read the power control register and set the 31*4882a593Smuzhiyun @ sleep force bit. 32*4882a593Smuzhiyun add r0, r6, #SIRFSOC_PWRC_PDN_CTRL 33*4882a593Smuzhiyun bl __sirfsoc_rtc_iobrg_readl 34*4882a593Smuzhiyun orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE 35*4882a593Smuzhiyun add r1, r6, #SIRFSOC_PWRC_PDN_CTRL 36*4882a593Smuzhiyun bl sirfsoc_rtc_iobrg_pre_writel 37*4882a593Smuzhiyun mov r1, #0x1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun @ read the MEM ctl register and set the self 40*4882a593Smuzhiyun @ refresh bit 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun ldr r2, [r5, #DENALI_CTL_22_OFF] 43*4882a593Smuzhiyun orr r2, r2, #0x1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun @ Following code has to run from cache since 46*4882a593Smuzhiyun @ the RAM is going to self refresh mode 47*4882a593Smuzhiyun .align 5 48*4882a593Smuzhiyun str r2, [r5, #DENALI_CTL_22_OFF] 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun1: 51*4882a593Smuzhiyun ldr r4, [r5, #DENALI_CTL_112_OFF] 52*4882a593Smuzhiyun tst r4, #0x1 53*4882a593Smuzhiyun bne 1b 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun @ write SLEEPFORCE through rtc iobridge 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun str r1, [r7] 58*4882a593Smuzhiyun @ wait rtc io bridge sync 59*4882a593Smuzhiyun1: 60*4882a593Smuzhiyun ldr r3, [r7] 61*4882a593Smuzhiyun tst r3, #0x01 62*4882a593Smuzhiyun bne 1b 63*4882a593Smuzhiyun b . 64