1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * reset controller for CSR SiRFprimaII
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/mutex.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/reboot.h>
17*4882a593Smuzhiyun #include <linux/reset-controller.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <asm/system_misc.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define SIRFSOC_RSTBIT_NUM 64
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static void __iomem *sirfsoc_rstc_base;
24*4882a593Smuzhiyun static DEFINE_MUTEX(rstc_lock);
25*4882a593Smuzhiyun
sirfsoc_reset_module(struct reset_controller_dev * rcdev,unsigned long sw_reset_idx)26*4882a593Smuzhiyun static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
27*4882a593Smuzhiyun unsigned long sw_reset_idx)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun u32 reset_bit = sw_reset_idx;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (reset_bit >= SIRFSOC_RSTBIT_NUM)
32*4882a593Smuzhiyun return -EINVAL;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun mutex_lock(&rstc_lock);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * Writing 1 to this bit resets corresponding block.
38*4882a593Smuzhiyun * Writing 0 to this bit de-asserts reset signal of the
39*4882a593Smuzhiyun * corresponding block. datasheet doesn't require explicit
40*4882a593Smuzhiyun * delay between the set and clear of reset bit. it could
41*4882a593Smuzhiyun * be shorter if tests pass.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun writel(readl(sirfsoc_rstc_base +
44*4882a593Smuzhiyun (reset_bit / 32) * 4) | (1 << reset_bit),
45*4882a593Smuzhiyun sirfsoc_rstc_base + (reset_bit / 32) * 4);
46*4882a593Smuzhiyun msleep(20);
47*4882a593Smuzhiyun writel(readl(sirfsoc_rstc_base +
48*4882a593Smuzhiyun (reset_bit / 32) * 4) & ~(1 << reset_bit),
49*4882a593Smuzhiyun sirfsoc_rstc_base + (reset_bit / 32) * 4);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun mutex_unlock(&rstc_lock);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static struct reset_control_ops sirfsoc_rstc_ops = {
57*4882a593Smuzhiyun .reset = sirfsoc_reset_module,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static struct reset_controller_dev sirfsoc_reset_controller = {
61*4882a593Smuzhiyun .ops = &sirfsoc_rstc_ops,
62*4882a593Smuzhiyun .nr_resets = SIRFSOC_RSTBIT_NUM,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define SIRFSOC_SYS_RST_BIT BIT(31)
66*4882a593Smuzhiyun
sirfsoc_restart(struct notifier_block * nb,unsigned long action,void * data)67*4882a593Smuzhiyun static int sirfsoc_restart(struct notifier_block *nb, unsigned long action,
68*4882a593Smuzhiyun void *data)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
71*4882a593Smuzhiyun return NOTIFY_DONE;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static struct notifier_block sirfsoc_restart_nb = {
75*4882a593Smuzhiyun .notifier_call = sirfsoc_restart,
76*4882a593Smuzhiyun .priority = 192,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
sirfsoc_rstc_probe(struct platform_device * pdev)79*4882a593Smuzhiyun static int sirfsoc_rstc_probe(struct platform_device *pdev)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
82*4882a593Smuzhiyun sirfsoc_rstc_base = of_iomap(np, 0);
83*4882a593Smuzhiyun if (!sirfsoc_rstc_base) {
84*4882a593Smuzhiyun dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
85*4882a593Smuzhiyun return -ENOMEM;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun sirfsoc_reset_controller.of_node = np;
89*4882a593Smuzhiyun register_restart_handler(&sirfsoc_restart_nb);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
92*4882a593Smuzhiyun reset_controller_register(&sirfsoc_reset_controller);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const struct of_device_id rstc_ids[] = {
98*4882a593Smuzhiyun { .compatible = "sirf,prima2-rstc" },
99*4882a593Smuzhiyun {},
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun static struct platform_driver sirfsoc_rstc_driver = {
103*4882a593Smuzhiyun .probe = sirfsoc_rstc_probe,
104*4882a593Smuzhiyun .driver = {
105*4882a593Smuzhiyun .name = "sirfsoc_rstc",
106*4882a593Smuzhiyun .of_match_table = rstc_ids,
107*4882a593Smuzhiyun },
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
sirfsoc_rstc_init(void)110*4882a593Smuzhiyun static int __init sirfsoc_rstc_init(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun return platform_driver_register(&sirfsoc_rstc_driver);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun subsys_initcall(sirfsoc_rstc_init);
115