1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * plat smp support for CSR Marco dual-core SMP SoCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/smp.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <asm/page.h>
14*4882a593Smuzhiyun #include <asm/mach/map.h>
15*4882a593Smuzhiyun #include <asm/smp_plat.h>
16*4882a593Smuzhiyun #include <asm/smp_scu.h>
17*4882a593Smuzhiyun #include <asm/cacheflush.h>
18*4882a593Smuzhiyun #include <asm/cputype.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "common.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static void __iomem *clk_base;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static DEFINE_SPINLOCK(boot_lock);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* XXX prima2_pen_release is cargo culted code - DO NOT COPY XXX */
27*4882a593Smuzhiyun volatile int prima2_pen_release = -1;
28*4882a593Smuzhiyun
sirfsoc_secondary_init(unsigned int cpu)29*4882a593Smuzhiyun static void sirfsoc_secondary_init(unsigned int cpu)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * let the primary processor know we're out of the
33*4882a593Smuzhiyun * pen, then head off into the C entry point
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun prima2_pen_release = -1;
36*4882a593Smuzhiyun smp_wmb();
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Synchronise with the boot thread.
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun spin_lock(&boot_lock);
42*4882a593Smuzhiyun spin_unlock(&boot_lock);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static const struct of_device_id clk_ids[] = {
46*4882a593Smuzhiyun { .compatible = "sirf,atlas7-clkc" },
47*4882a593Smuzhiyun {},
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
sirfsoc_boot_secondary(unsigned int cpu,struct task_struct * idle)50*4882a593Smuzhiyun static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun unsigned long timeout;
53*4882a593Smuzhiyun struct device_node *np;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun np = of_find_matching_node(NULL, clk_ids);
56*4882a593Smuzhiyun if (!np)
57*4882a593Smuzhiyun return -ENODEV;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun clk_base = of_iomap(np, 0);
60*4882a593Smuzhiyun if (!clk_base)
61*4882a593Smuzhiyun return -ENOMEM;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * write the address of secondary startup into the clkc register
65*4882a593Smuzhiyun * at offset 0x2bC, then write the magic number 0x3CAF5D62 to the
66*4882a593Smuzhiyun * clkc register at offset 0x2b8, which is what boot rom code is
67*4882a593Smuzhiyun * waiting for. This would wake up the secondary core from WFE
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
70*4882a593Smuzhiyun __raw_writel(__pa_symbol(sirfsoc_secondary_startup),
71*4882a593Smuzhiyun clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
74*4882a593Smuzhiyun __raw_writel(0x3CAF5D62,
75*4882a593Smuzhiyun clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* make sure write buffer is drained */
78*4882a593Smuzhiyun mb();
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun spin_lock(&boot_lock);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * The secondary processor is waiting to be released from
84*4882a593Smuzhiyun * the holding pen - release it, then wait for it to flag
85*4882a593Smuzhiyun * that it has been released by resetting prima2_pen_release.
86*4882a593Smuzhiyun *
87*4882a593Smuzhiyun * Note that "prima2_pen_release" is the hardware CPU ID, whereas
88*4882a593Smuzhiyun * "cpu" is Linux's internal ID.
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun prima2_pen_release = cpu_logical_map(cpu);
91*4882a593Smuzhiyun sync_cache_w(&prima2_pen_release);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun * Send the secondary CPU SEV, thereby causing the boot monitor to read
95*4882a593Smuzhiyun * the JUMPADDR and WAKEMAGIC, and branch to the address found there.
96*4882a593Smuzhiyun */
97*4882a593Smuzhiyun dsb_sev();
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun timeout = jiffies + (1 * HZ);
100*4882a593Smuzhiyun while (time_before(jiffies, timeout)) {
101*4882a593Smuzhiyun smp_rmb();
102*4882a593Smuzhiyun if (prima2_pen_release == -1)
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun udelay(10);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun * now the secondary core is starting up let it run its
110*4882a593Smuzhiyun * calibrations, then wait for it to finish
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun spin_unlock(&boot_lock);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return prima2_pen_release != -1 ? -ENOSYS : 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun const struct smp_operations sirfsoc_smp_ops __initconst = {
118*4882a593Smuzhiyun .smp_secondary_init = sirfsoc_secondary_init,
119*4882a593Smuzhiyun .smp_boot_secondary = sirfsoc_boot_secondary,
120*4882a593Smuzhiyun #ifdef CONFIG_HOTPLUG_CPU
121*4882a593Smuzhiyun .cpu_die = sirfsoc_cpu_die,
122*4882a593Smuzhiyun #endif
123*4882a593Smuzhiyun };
124