1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
4*4882a593Smuzhiyun * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
5*4882a593Smuzhiyun * Copyright (C) 2002 ARM Ltd.
6*4882a593Smuzhiyun * All Rights Reserved
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/cacheflush.h>
14*4882a593Smuzhiyun #include <asm/cp15.h>
15*4882a593Smuzhiyun #include <asm/smp_plat.h>
16*4882a593Smuzhiyun #include <asm/smp_scu.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun extern void ox820_secondary_startup(void);
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static void __iomem *cpu_ctrl;
21*4882a593Smuzhiyun static void __iomem *gic_cpu_ctrl;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define HOLDINGPEN_CPU_OFFSET 0xc8
24*4882a593Smuzhiyun #define HOLDINGPEN_LOCATION_OFFSET 0xc4
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100)
27*4882a593Smuzhiyun #define GIC_CPU_CTRL 0x00
28*4882a593Smuzhiyun #define GIC_CPU_CTRL_ENABLE 1
29*4882a593Smuzhiyun
ox820_boot_secondary(unsigned int cpu,struct task_struct * idle)30*4882a593Smuzhiyun static int __init ox820_boot_secondary(unsigned int cpu,
31*4882a593Smuzhiyun struct task_struct *idle)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * Write the address of secondary startup into the
35*4882a593Smuzhiyun * system-wide flags register. The BootMonitor waits
36*4882a593Smuzhiyun * until it receives a soft interrupt, and then the
37*4882a593Smuzhiyun * secondary CPU branches to this address.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun writel(virt_to_phys(ox820_secondary_startup),
40*4882a593Smuzhiyun cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * Enable GIC cpu interface in CPU Interface Control Register
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun writel(GIC_CPU_CTRL_ENABLE,
48*4882a593Smuzhiyun gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * Send the secondary CPU a soft interrupt, thereby causing
52*4882a593Smuzhiyun * the boot monitor to read the system wide flags register,
53*4882a593Smuzhiyun * and branch to the address found there.
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun arch_send_wakeup_ipi_mask(cpumask_of(cpu));
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
ox820_smp_prepare_cpus(unsigned int max_cpus)60*4882a593Smuzhiyun static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct device_node *np;
63*4882a593Smuzhiyun void __iomem *scu_base;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
66*4882a593Smuzhiyun scu_base = of_iomap(np, 0);
67*4882a593Smuzhiyun of_node_put(np);
68*4882a593Smuzhiyun if (!scu_base)
69*4882a593Smuzhiyun return;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Remap CPU Interrupt Interface Registers */
72*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
73*4882a593Smuzhiyun gic_cpu_ctrl = of_iomap(np, 1);
74*4882a593Smuzhiyun of_node_put(np);
75*4882a593Smuzhiyun if (!gic_cpu_ctrl)
76*4882a593Smuzhiyun goto unmap_scu;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
79*4882a593Smuzhiyun cpu_ctrl = of_iomap(np, 0);
80*4882a593Smuzhiyun of_node_put(np);
81*4882a593Smuzhiyun if (!cpu_ctrl)
82*4882a593Smuzhiyun goto unmap_scu;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun scu_enable(scu_base);
85*4882a593Smuzhiyun flush_cache_all();
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun unmap_scu:
88*4882a593Smuzhiyun iounmap(scu_base);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static const struct smp_operations ox820_smp_ops __initconst = {
92*4882a593Smuzhiyun .smp_prepare_cpus = ox820_smp_prepare_cpus,
93*4882a593Smuzhiyun .smp_boot_secondary = ox820_boot_secondary,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);
97