xref: /OK3568_Linux_fs/kernel/arch/arm/mach-orion5x/wrt350n-v2-setup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * arch/arm/mach-orion5x/wrt350n-v2-setup.c
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This file is licensed under the terms of the GNU General Public
5*4882a593Smuzhiyun  * License version 2.  This program is licensed "as is" without any
6*4882a593Smuzhiyun  * warranty of any kind, whether express or implied.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #include <linux/gpio.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/pci.h>
13*4882a593Smuzhiyun #include <linux/irq.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
16*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
17*4882a593Smuzhiyun #include <linux/ethtool.h>
18*4882a593Smuzhiyun #include <linux/leds.h>
19*4882a593Smuzhiyun #include <linux/gpio_keys.h>
20*4882a593Smuzhiyun #include <linux/input.h>
21*4882a593Smuzhiyun #include <linux/platform_data/dsa.h>
22*4882a593Smuzhiyun #include <asm/mach-types.h>
23*4882a593Smuzhiyun #include <asm/mach/arch.h>
24*4882a593Smuzhiyun #include <asm/mach/pci.h>
25*4882a593Smuzhiyun #include "orion5x.h"
26*4882a593Smuzhiyun #include "common.h"
27*4882a593Smuzhiyun #include "mpp.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun  * LEDs attached to GPIO
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun static struct gpio_led wrt350n_v2_led_pins[] = {
33*4882a593Smuzhiyun 	{
34*4882a593Smuzhiyun 		.name		= "wrt350nv2:green:power",
35*4882a593Smuzhiyun 		.gpio		= 0,
36*4882a593Smuzhiyun 		.active_low	= 1,
37*4882a593Smuzhiyun 	}, {
38*4882a593Smuzhiyun 		.name		= "wrt350nv2:green:security",
39*4882a593Smuzhiyun 		.gpio		= 1,
40*4882a593Smuzhiyun 		.active_low	= 1,
41*4882a593Smuzhiyun 	}, {
42*4882a593Smuzhiyun 		.name		= "wrt350nv2:orange:power",
43*4882a593Smuzhiyun 		.gpio		= 5,
44*4882a593Smuzhiyun 		.active_low	= 1,
45*4882a593Smuzhiyun 	}, {
46*4882a593Smuzhiyun 		.name		= "wrt350nv2:green:usb",
47*4882a593Smuzhiyun 		.gpio		= 6,
48*4882a593Smuzhiyun 		.active_low	= 1,
49*4882a593Smuzhiyun 	}, {
50*4882a593Smuzhiyun 		.name		= "wrt350nv2:green:wireless",
51*4882a593Smuzhiyun 		.gpio		= 7,
52*4882a593Smuzhiyun 		.active_low	= 1,
53*4882a593Smuzhiyun 	},
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun static struct gpio_led_platform_data wrt350n_v2_led_data = {
57*4882a593Smuzhiyun 	.leds		= wrt350n_v2_led_pins,
58*4882a593Smuzhiyun 	.num_leds	= ARRAY_SIZE(wrt350n_v2_led_pins),
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun static struct platform_device wrt350n_v2_leds = {
62*4882a593Smuzhiyun 	.name	= "leds-gpio",
63*4882a593Smuzhiyun 	.id	= -1,
64*4882a593Smuzhiyun 	.dev	= {
65*4882a593Smuzhiyun 		.platform_data	= &wrt350n_v2_led_data,
66*4882a593Smuzhiyun 	},
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun  * Buttons attached to GPIO
71*4882a593Smuzhiyun  */
72*4882a593Smuzhiyun static struct gpio_keys_button wrt350n_v2_buttons[] = {
73*4882a593Smuzhiyun 	{
74*4882a593Smuzhiyun 		.code		= KEY_RESTART,
75*4882a593Smuzhiyun 		.gpio		= 3,
76*4882a593Smuzhiyun 		.desc		= "Reset Button",
77*4882a593Smuzhiyun 		.active_low	= 1,
78*4882a593Smuzhiyun 	}, {
79*4882a593Smuzhiyun 		.code		= KEY_WPS_BUTTON,
80*4882a593Smuzhiyun 		.gpio		= 2,
81*4882a593Smuzhiyun 		.desc		= "WPS Button",
82*4882a593Smuzhiyun 		.active_low	= 1,
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static struct gpio_keys_platform_data wrt350n_v2_button_data = {
87*4882a593Smuzhiyun 	.buttons	= wrt350n_v2_buttons,
88*4882a593Smuzhiyun 	.nbuttons	= ARRAY_SIZE(wrt350n_v2_buttons),
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun static struct platform_device wrt350n_v2_button_device = {
92*4882a593Smuzhiyun 	.name		= "gpio-keys",
93*4882a593Smuzhiyun 	.id		= -1,
94*4882a593Smuzhiyun 	.num_resources	= 0,
95*4882a593Smuzhiyun 	.dev		= {
96*4882a593Smuzhiyun 		.platform_data	= &wrt350n_v2_button_data,
97*4882a593Smuzhiyun 	},
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /*
101*4882a593Smuzhiyun  * General setup
102*4882a593Smuzhiyun  */
103*4882a593Smuzhiyun static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
104*4882a593Smuzhiyun 	MPP0_GPIO,		/* Power LED green (0=on) */
105*4882a593Smuzhiyun 	MPP1_GPIO,		/* Security LED (0=on) */
106*4882a593Smuzhiyun 	MPP2_GPIO,		/* Internal Button (0=on) */
107*4882a593Smuzhiyun 	MPP3_GPIO,		/* Reset Button (0=on) */
108*4882a593Smuzhiyun 	MPP4_GPIO,		/* PCI int */
109*4882a593Smuzhiyun 	MPP5_GPIO,		/* Power LED orange (0=on) */
110*4882a593Smuzhiyun 	MPP6_GPIO,		/* USB LED (0=on) */
111*4882a593Smuzhiyun 	MPP7_GPIO,		/* Wireless LED (0=on) */
112*4882a593Smuzhiyun 	MPP8_UNUSED,		/* ??? */
113*4882a593Smuzhiyun 	MPP9_GIGE,		/* GE_RXERR */
114*4882a593Smuzhiyun 	MPP10_UNUSED,		/* ??? */
115*4882a593Smuzhiyun 	MPP11_UNUSED,		/* ??? */
116*4882a593Smuzhiyun 	MPP12_GIGE,		/* GE_TXD[4] */
117*4882a593Smuzhiyun 	MPP13_GIGE,		/* GE_TXD[5] */
118*4882a593Smuzhiyun 	MPP14_GIGE,		/* GE_TXD[6] */
119*4882a593Smuzhiyun 	MPP15_GIGE,		/* GE_TXD[7] */
120*4882a593Smuzhiyun 	MPP16_GIGE,		/* GE_RXD[4] */
121*4882a593Smuzhiyun 	MPP17_GIGE,		/* GE_RXD[5] */
122*4882a593Smuzhiyun 	MPP18_GIGE,		/* GE_RXD[6] */
123*4882a593Smuzhiyun 	MPP19_GIGE,		/* GE_RXD[7] */
124*4882a593Smuzhiyun 	0,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun /*
128*4882a593Smuzhiyun  * 8M NOR flash Device bus boot chip select
129*4882a593Smuzhiyun  */
130*4882a593Smuzhiyun #define WRT350N_V2_NOR_BOOT_BASE	0xf4000000
131*4882a593Smuzhiyun #define WRT350N_V2_NOR_BOOT_SIZE	SZ_8M
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
134*4882a593Smuzhiyun 	{
135*4882a593Smuzhiyun 		.name		= "kernel",
136*4882a593Smuzhiyun 		.offset		= 0x00000000,
137*4882a593Smuzhiyun 		.size		= 0x00760000,
138*4882a593Smuzhiyun 	}, {
139*4882a593Smuzhiyun 		.name		= "rootfs",
140*4882a593Smuzhiyun 		.offset		= 0x001a0000,
141*4882a593Smuzhiyun 		.size		= 0x005c0000,
142*4882a593Smuzhiyun 	}, {
143*4882a593Smuzhiyun 		.name		= "lang",
144*4882a593Smuzhiyun 		.offset		= 0x00760000,
145*4882a593Smuzhiyun 		.size		= 0x00040000,
146*4882a593Smuzhiyun 	}, {
147*4882a593Smuzhiyun 		.name		= "nvram",
148*4882a593Smuzhiyun 		.offset		= 0x007a0000,
149*4882a593Smuzhiyun 		.size		= 0x00020000,
150*4882a593Smuzhiyun 	}, {
151*4882a593Smuzhiyun 		.name		= "u-boot",
152*4882a593Smuzhiyun 		.offset		= 0x007c0000,
153*4882a593Smuzhiyun 		.size		= 0x00040000,
154*4882a593Smuzhiyun 	},
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
158*4882a593Smuzhiyun 	.width		= 1,
159*4882a593Smuzhiyun 	.parts		= wrt350n_v2_nor_flash_partitions,
160*4882a593Smuzhiyun 	.nr_parts	= ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static struct resource wrt350n_v2_nor_flash_resource = {
164*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
165*4882a593Smuzhiyun 	.start		= WRT350N_V2_NOR_BOOT_BASE,
166*4882a593Smuzhiyun 	.end		= WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun static struct platform_device wrt350n_v2_nor_flash = {
170*4882a593Smuzhiyun 	.name			= "physmap-flash",
171*4882a593Smuzhiyun 	.id			= 0,
172*4882a593Smuzhiyun 	.dev		= {
173*4882a593Smuzhiyun 		.platform_data	= &wrt350n_v2_nor_flash_data,
174*4882a593Smuzhiyun 	},
175*4882a593Smuzhiyun 	.num_resources		= 1,
176*4882a593Smuzhiyun 	.resource		= &wrt350n_v2_nor_flash_resource,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
180*4882a593Smuzhiyun 	.phy_addr	= MV643XX_ETH_PHY_NONE,
181*4882a593Smuzhiyun 	.speed		= SPEED_1000,
182*4882a593Smuzhiyun 	.duplex		= DUPLEX_FULL,
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun static struct dsa_chip_data wrt350n_v2_switch_chip_data = {
186*4882a593Smuzhiyun 	.port_names[0]	= "lan2",
187*4882a593Smuzhiyun 	.port_names[1]	= "lan1",
188*4882a593Smuzhiyun 	.port_names[2]	= "wan",
189*4882a593Smuzhiyun 	.port_names[3]	= "cpu",
190*4882a593Smuzhiyun 	.port_names[5]	= "lan3",
191*4882a593Smuzhiyun 	.port_names[7]	= "lan4",
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
wrt350n_v2_init(void)194*4882a593Smuzhiyun static void __init wrt350n_v2_init(void)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	/*
197*4882a593Smuzhiyun 	 * Setup basic Orion functions. Need to be called early.
198*4882a593Smuzhiyun 	 */
199*4882a593Smuzhiyun 	orion5x_init();
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	orion5x_mpp_conf(wrt350n_v2_mpp_modes);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	/*
204*4882a593Smuzhiyun 	 * Configure peripherals.
205*4882a593Smuzhiyun 	 */
206*4882a593Smuzhiyun 	orion5x_ehci0_init();
207*4882a593Smuzhiyun 	orion5x_eth_init(&wrt350n_v2_eth_data);
208*4882a593Smuzhiyun 	orion5x_eth_switch_init(&wrt350n_v2_switch_chip_data);
209*4882a593Smuzhiyun 	orion5x_uart0_init();
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
212*4882a593Smuzhiyun 				    ORION_MBUS_DEVBUS_BOOT_ATTR,
213*4882a593Smuzhiyun 				    WRT350N_V2_NOR_BOOT_BASE,
214*4882a593Smuzhiyun 				    WRT350N_V2_NOR_BOOT_SIZE);
215*4882a593Smuzhiyun 	platform_device_register(&wrt350n_v2_nor_flash);
216*4882a593Smuzhiyun 	platform_device_register(&wrt350n_v2_leds);
217*4882a593Smuzhiyun 	platform_device_register(&wrt350n_v2_button_device);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
wrt350n_v2_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)220*4882a593Smuzhiyun static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot,
221*4882a593Smuzhiyun 	u8 pin)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun 	int irq;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	/*
226*4882a593Smuzhiyun 	 * Check for devices with hard-wired IRQs.
227*4882a593Smuzhiyun 	 */
228*4882a593Smuzhiyun 	irq = orion5x_pci_map_irq(dev, slot, pin);
229*4882a593Smuzhiyun 	if (irq != -1)
230*4882a593Smuzhiyun 		return irq;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	/*
233*4882a593Smuzhiyun 	 * Mini-PCI slot.
234*4882a593Smuzhiyun 	 */
235*4882a593Smuzhiyun 	if (slot == 7)
236*4882a593Smuzhiyun 		return gpio_to_irq(4);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	return -1;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun static struct hw_pci wrt350n_v2_pci __initdata = {
242*4882a593Smuzhiyun 	.nr_controllers	= 2,
243*4882a593Smuzhiyun 	.setup		= orion5x_pci_sys_setup,
244*4882a593Smuzhiyun 	.scan		= orion5x_pci_sys_scan_bus,
245*4882a593Smuzhiyun 	.map_irq	= wrt350n_v2_pci_map_irq,
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun 
wrt350n_v2_pci_init(void)248*4882a593Smuzhiyun static int __init wrt350n_v2_pci_init(void)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun 	if (machine_is_wrt350n_v2())
251*4882a593Smuzhiyun 		pci_common_init(&wrt350n_v2_pci);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	return 0;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun subsys_initcall(wrt350n_v2_pci_init);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
258*4882a593Smuzhiyun 	/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
259*4882a593Smuzhiyun 	.atag_offset	= 0x100,
260*4882a593Smuzhiyun 	.nr_irqs	= ORION5X_NR_IRQS,
261*4882a593Smuzhiyun 	.init_machine	= wrt350n_v2_init,
262*4882a593Smuzhiyun 	.map_io		= orion5x_map_io,
263*4882a593Smuzhiyun 	.init_early	= orion5x_init_early,
264*4882a593Smuzhiyun 	.init_irq	= orion5x_init_irq,
265*4882a593Smuzhiyun 	.init_time	= orion5x_timer_init,
266*4882a593Smuzhiyun 	.fixup		= tag_fixup_mem32,
267*4882a593Smuzhiyun 	.restart	= orion5x_restart,
268*4882a593Smuzhiyun MACHINE_END
269