1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-orion5x/wnr854t-setup.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
6*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/gpio.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/pci.h>
13*4882a593Smuzhiyun #include <linux/irq.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
16*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
17*4882a593Smuzhiyun #include <linux/ethtool.h>
18*4882a593Smuzhiyun #include <linux/platform_data/dsa.h>
19*4882a593Smuzhiyun #include <asm/mach-types.h>
20*4882a593Smuzhiyun #include <asm/mach/arch.h>
21*4882a593Smuzhiyun #include <asm/mach/pci.h>
22*4882a593Smuzhiyun #include "orion5x.h"
23*4882a593Smuzhiyun #include "common.h"
24*4882a593Smuzhiyun #include "mpp.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static unsigned int wnr854t_mpp_modes[] __initdata = {
27*4882a593Smuzhiyun MPP0_GPIO, /* Power LED green (0=on) */
28*4882a593Smuzhiyun MPP1_GPIO, /* Reset Button (0=off) */
29*4882a593Smuzhiyun MPP2_GPIO, /* Power LED blink (0=off) */
30*4882a593Smuzhiyun MPP3_GPIO, /* WAN Status LED amber (0=off) */
31*4882a593Smuzhiyun MPP4_GPIO, /* PCI int */
32*4882a593Smuzhiyun MPP5_GPIO, /* ??? */
33*4882a593Smuzhiyun MPP6_GPIO, /* ??? */
34*4882a593Smuzhiyun MPP7_GPIO, /* ??? */
35*4882a593Smuzhiyun MPP8_UNUSED, /* ??? */
36*4882a593Smuzhiyun MPP9_GIGE, /* GE_RXERR */
37*4882a593Smuzhiyun MPP10_UNUSED, /* ??? */
38*4882a593Smuzhiyun MPP11_UNUSED, /* ??? */
39*4882a593Smuzhiyun MPP12_GIGE, /* GE_TXD[4] */
40*4882a593Smuzhiyun MPP13_GIGE, /* GE_TXD[5] */
41*4882a593Smuzhiyun MPP14_GIGE, /* GE_TXD[6] */
42*4882a593Smuzhiyun MPP15_GIGE, /* GE_TXD[7] */
43*4882a593Smuzhiyun MPP16_GIGE, /* GE_RXD[4] */
44*4882a593Smuzhiyun MPP17_GIGE, /* GE_RXD[5] */
45*4882a593Smuzhiyun MPP18_GIGE, /* GE_RXD[6] */
46*4882a593Smuzhiyun MPP19_GIGE, /* GE_RXD[7] */
47*4882a593Smuzhiyun 0,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * 8M NOR flash Device bus boot chip select
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun #define WNR854T_NOR_BOOT_BASE 0xf4000000
54*4882a593Smuzhiyun #define WNR854T_NOR_BOOT_SIZE SZ_8M
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static struct mtd_partition wnr854t_nor_flash_partitions[] = {
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun .name = "kernel",
59*4882a593Smuzhiyun .offset = 0x00000000,
60*4882a593Smuzhiyun .size = 0x00100000,
61*4882a593Smuzhiyun }, {
62*4882a593Smuzhiyun .name = "rootfs",
63*4882a593Smuzhiyun .offset = 0x00100000,
64*4882a593Smuzhiyun .size = 0x00660000,
65*4882a593Smuzhiyun }, {
66*4882a593Smuzhiyun .name = "uboot",
67*4882a593Smuzhiyun .offset = 0x00760000,
68*4882a593Smuzhiyun .size = 0x00040000,
69*4882a593Smuzhiyun },
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static struct physmap_flash_data wnr854t_nor_flash_data = {
73*4882a593Smuzhiyun .width = 2,
74*4882a593Smuzhiyun .parts = wnr854t_nor_flash_partitions,
75*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions),
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static struct resource wnr854t_nor_flash_resource = {
79*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
80*4882a593Smuzhiyun .start = WNR854T_NOR_BOOT_BASE,
81*4882a593Smuzhiyun .end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static struct platform_device wnr854t_nor_flash = {
85*4882a593Smuzhiyun .name = "physmap-flash",
86*4882a593Smuzhiyun .id = 0,
87*4882a593Smuzhiyun .dev = {
88*4882a593Smuzhiyun .platform_data = &wnr854t_nor_flash_data,
89*4882a593Smuzhiyun },
90*4882a593Smuzhiyun .num_resources = 1,
91*4882a593Smuzhiyun .resource = &wnr854t_nor_flash_resource,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static struct mv643xx_eth_platform_data wnr854t_eth_data = {
95*4882a593Smuzhiyun .phy_addr = MV643XX_ETH_PHY_NONE,
96*4882a593Smuzhiyun .speed = SPEED_1000,
97*4882a593Smuzhiyun .duplex = DUPLEX_FULL,
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static struct dsa_chip_data wnr854t_switch_chip_data = {
101*4882a593Smuzhiyun .port_names[0] = "lan3",
102*4882a593Smuzhiyun .port_names[1] = "lan4",
103*4882a593Smuzhiyun .port_names[2] = "wan",
104*4882a593Smuzhiyun .port_names[3] = "cpu",
105*4882a593Smuzhiyun .port_names[5] = "lan1",
106*4882a593Smuzhiyun .port_names[7] = "lan2",
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
wnr854t_init(void)109*4882a593Smuzhiyun static void __init wnr854t_init(void)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun * Setup basic Orion functions. Need to be called early.
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun orion5x_init();
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun orion5x_mpp_conf(wnr854t_mpp_modes);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /*
119*4882a593Smuzhiyun * Configure peripherals.
120*4882a593Smuzhiyun */
121*4882a593Smuzhiyun orion5x_eth_init(&wnr854t_eth_data);
122*4882a593Smuzhiyun orion5x_eth_switch_init(&wnr854t_switch_chip_data);
123*4882a593Smuzhiyun orion5x_uart0_init();
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
126*4882a593Smuzhiyun ORION_MBUS_DEVBUS_BOOT_ATTR,
127*4882a593Smuzhiyun WNR854T_NOR_BOOT_BASE,
128*4882a593Smuzhiyun WNR854T_NOR_BOOT_SIZE);
129*4882a593Smuzhiyun platform_device_register(&wnr854t_nor_flash);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
wnr854t_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)132*4882a593Smuzhiyun static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
133*4882a593Smuzhiyun u8 pin)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun int irq;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /*
138*4882a593Smuzhiyun * Check for devices with hard-wired IRQs.
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun irq = orion5x_pci_map_irq(dev, slot, pin);
141*4882a593Smuzhiyun if (irq != -1)
142*4882a593Smuzhiyun return irq;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /*
145*4882a593Smuzhiyun * Mini-PCI slot.
146*4882a593Smuzhiyun */
147*4882a593Smuzhiyun if (slot == 7)
148*4882a593Smuzhiyun return gpio_to_irq(4);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun return -1;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static struct hw_pci wnr854t_pci __initdata = {
154*4882a593Smuzhiyun .nr_controllers = 2,
155*4882a593Smuzhiyun .setup = orion5x_pci_sys_setup,
156*4882a593Smuzhiyun .scan = orion5x_pci_sys_scan_bus,
157*4882a593Smuzhiyun .map_irq = wnr854t_pci_map_irq,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
wnr854t_pci_init(void)160*4882a593Smuzhiyun static int __init wnr854t_pci_init(void)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun if (machine_is_wnr854t())
163*4882a593Smuzhiyun pci_common_init(&wnr854t_pci);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun subsys_initcall(wnr854t_pci_init);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun MACHINE_START(WNR854T, "Netgear WNR854T")
170*4882a593Smuzhiyun /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
171*4882a593Smuzhiyun .atag_offset = 0x100,
172*4882a593Smuzhiyun .nr_irqs = ORION5X_NR_IRQS,
173*4882a593Smuzhiyun .init_machine = wnr854t_init,
174*4882a593Smuzhiyun .map_io = orion5x_map_io,
175*4882a593Smuzhiyun .init_early = orion5x_init_early,
176*4882a593Smuzhiyun .init_irq = orion5x_init_irq,
177*4882a593Smuzhiyun .init_time = orion5x_timer_init,
178*4882a593Smuzhiyun .fixup = tag_fixup_mem32,
179*4882a593Smuzhiyun .restart = orion5x_restart,
180*4882a593Smuzhiyun MACHINE_END
181